74F161ASJ Fairchild Semiconductor, 74F161ASJ Datasheet - Page 3

• Manufacturer Part Number: 74F161ASJ
• Description: IC BINARY COUNTER SYNC 16SOP
• Manufacturer: Fairchild Semiconductor
• Series: 74Fr

Specifications of 74F161ASJ

• Logic Type: Binary Counter
• Direction: Up
• Number Of Elements: 1
• Number Of Bits Per Element: 4
• Reset: Asynchronous
• Timing: Synchronous
• Count Rate: 120MHz
• Trigger Type: Positive Edge
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (5.3mm Width), 16-SO, 16-SOEIIJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
Functional Description
The 74F161A and 74F163A count in modulo-16 binary
sequence. From state 15 (HHHH) they increment to
state 0 (LLLL). The clock inputs of all flip-flops are driven
in parallel through a clock buffer. Thus all changes of the
Q outputs (except due to Master Reset of the 74F161A)
occur as a result of, and synchronous with, the LOW-to-
HIGH transition of the CP input signal. The circuits have
four fundamental modes of operation, in order of prece-
dence: asynchronous reset (74F161A), synchronous
reset (74F163A), parallel load, count-up and hold. Five
control inputs—Master Reset (MR, 74F161A), Synchro-
nous Reset (SR, 74F163A), Parallel Enable (PE), Count
Enable Parallel (CEP) and Count Enable Trickle (CET)—
determine the mode of operation, as shown in the Mode
Select Table. A LOW signal on MR overrides all other
inputs and asynchronously forces all outputs LOW. A
LOW signal on SR overrides counting and parallel load-
ing and allows all outputs to go LOW on the next rising
edge of CP. A LOW signal on PE overrides counting and
allows information on the Parallel Data (P
loaded into the flip-flops on the next rising edge of CP.
With PE and MR ('F161A) or SR (74F163A) HIGH, CEP
and CET permit counting when both are HIGH. Con-
versely, a LOW signal on either CEP or CET inhibits
counting.
The 74F161A and 74F163A use D-type edge triggered
flip-flops and changing the SR, PE, CEP and CET inputs
when the CP is in either state does not cause errors, pro-
vided that the recommended setup and hold times, with
respect to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and the counter is in state 15. To implement syn-
chronous multi-stage counters, the TC outputs can be
used with the CEP and CET inputs in two different ways.
Please refer to the 74F568 data sheet. The TC output is
subject to decoding spikes due to internal race condi-
tions and is therefore not recommended for use as a
clock or asynchronous reset for flip-flops, counters or
registers.
n
) inputs to be
3
Logic Equations:
Count Enable = CEP • CET • PE
TC = Q
Mode Select Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Note:
1. For 74F163A only
State Diagram
SR
H
H
H
H
L
(1)
0
• Q
PE
H
H
H
X
L
1
• Q
CET CEP
2
X
X
H
X
L
• Q
3
• CET
X
X
H
X
L
Reset (Clear)
Load (P
Count (Increment)
No Change (Hold)
No Change (Hold)
Action on the Rising
Clock Edge (
n
→ Q
www.fairchildsemi.com
n
)
)