TS256MBCF45I-D Transcend Information. Inc., TS256MBCF45I-D Datasheet - Page 15

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TS256MBCF45I-D

Manufacturer Part Number
TS256MBCF45I-D
Description
Transcend Industrial Cf Card
Manufacturer
Transcend Information. Inc.
Datasheet
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Transcend Information Inc.
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Additional Requirements for CF Advanced Timing Modes
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Notes: 1) Control Signals: each card shall present a load to the socket no larger than 50 pF
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2) Resistor is optional.
3) Status Signals: the socket shall present a load to the card no larger than 50 pF
4) Status Signals: the socket shall present a load to the card no larger than 50 pF
5) Status Signals: the socket shall present a load to the card no larger than 50 pF
6) BVD2 was not defined in the JEIDA 3.0 release. Systems fully supporting JEIDA release 3 SRAM cards shall
7) Address Signals: each card shall present a load of no more than 100pF
8) Data Signals: the host and each card shall present a load no larger than 50pF
9) Reset Signal: This signal is pulled up to prevent the input from floating when a CFA to PCMCIA adapter is used in
10) Host and card restrictions for CF Advanced Timing Modes and Ultra DMA modes: Additional Requirements for
The CF Advanced Timing modes include PCMCIA I/O and Memory modes that are 100ns or faster and True
IDE PIO Modes 5,6 and Multiword DMA Modes 3,4.
When operating in CF Advanced timing modes, the host shall conform to the following requirements:
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state and 150 μA high state, including pull-resistor. The socket shall be able to drive at least the following load
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current 700 μA low state and 150 μA high state per socket).
state and 100 μA high state, including pull-up resistor. The card shall be able to drive at least the following load
10
state and 100 μA high state, including pull-up resistor. The card shall be able to drive at least the following load
10
state and 100 μA high state, including pull-up resistor. The card shall be able to drive at least the following load
10
pull-up pin 45 (BVD2) to avoid sensing their batteries as “Low.”
150μA high state. The host shall be able to drive at least the following load
requirements: (the number of sockets wired in parallel) multiplied by (100pF with DC current 450μA low state
and 150μA high state per socket).
150μA high state. The host and each card shall be able to drive at least the following load
timing requirements: 100pF with DC current 1.6mA low state and 300μA high state. This permits the host to wire
two sockets in parallel without derating the card access speeds.
a PCMCIA revision 1 host. However, to minimize DC current drain through the pull-up resistor in normal
operation the pull-up should be turned off once the Reset signal has been actively driven low by the host.
Consequently, the input is specified as an I2Z because the resistor is not necessarily detectable in the input
current leakage test.
CF Advanced Timing Modes and Ultra DMA Electrical Requirements for additional required limitations on the
implementation of CF Advanced Timing modes and Ultra DMA modes respectively.
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while meeting all AC timing requirements: (the number of sockets wired in parallel) multiplied by (50 pF with DC
while meeting all AC timing requirements: 50 pF at a DC current of 400 μA low state and 100 μA high state.
while meeting all AC timing requirements: 50 pF at a DC current of 400 μA low state and 100 μA high state.
while meeting all AC timing requirements: 50 pF at a DC current of 400 μA low state and 1100 μA high state.
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Only one CF device shall be attached to the CF Bus.
The host shall not present a load of more than 40pF to the device for all signals, including any cabling.
The maximum cable length is 0.15 m (6 in). The cable length is measured from the card connector to the host
controller. 0.46 m (18 in) cables are not supported.
The -WAIT and IORDY signals shall be ignored by the host. Devices supporting CF Advanced timing modes
shall also support slower timing modes, to ensure operability with systems that do not support CF Advanced
timing modes
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at a DC current of 450μA low state and
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while meeting all AC timing
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at a DC current of 450μA and
at a DC current of 400 μA low
at a DC current of 400 μA low
at a DC current of 400 μA low
at a DC current of 700 μA low
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while meeting all AC
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