MC14017BCPG ON Semiconductor, MC14017BCPG Datasheet - Page 5

• Manufacturer Part Number: MC14017BCPG
• Description: IC COUNTER/DIVIDER DECADE 16DIP
• Manufacturer: ON Semiconductor
• Series: 4000Br

Specifications of MC14017BCPG

• Logic Type: Counter, Decade
• Direction: Up
• Number Of Elements: 1
• Number Of Bits Per Element: 10
• Reset: Asynchronous
• Count Rate: 16MHz
• Trigger Type: Positive Edge
• Voltage - Supply: 3 V ~ 18 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Counter Type: Decade
• Counting Sequence: Up
• Number Of Circuits: 1
• Logic Family: 14017
• Propagation Delay Time: 1000 ns, 460 ns, 350 ns
• Supply Voltage (max): 18 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Function: Counter/Divider
• Mounting Style: Through Hole
• Operating Supply Voltage: 3 V to 18 V
• Circuit Type: Low-Power Schottky
• Current, Supply: 600 μA
• Function Type: 5-Stages
• Logic Function: Counter
• Package Type: PDIP-16
• Special Features: Decade
• Temperature, Operating, Range: -55 to +125 °C
• Voltage, Supply: 3 to 18 VDC
• Clock Frequency: 16MHz
• Count Maximum: 5
• Supply Voltage Range: 3V To 18V
• Logic Case Style: DIP
• No. Of Pins: 16
• Operating Temperature Range: -55°C To +125°C
• Filter Terminals: DIP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Timing: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: MC14017BCPGOS

V
V
V
DD
SS
SS
GENERATOR
PULSE
A
B
S1
S1
500 mF
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
f
c
CLOCK
ENABLE
RESET
CLOCK C
V
V
DD
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
SS
out
Figure 2. Typical Power Dissipation Test Circuit
CLOCK
ENABLE
RESET
CLOCK
I
D
V
V
DD
SS
C
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
out
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0.01 mF
CERAMIC
EXTERNAL
MC14017B
POWER
SUPPLY
I
D
C
V
L
5
out
C
L
C
L
C
L
Outputs
Decode
C
V
V
Carry
L
GS
DS
=
=
C
L
Sink Drive
Clock to 5
(S1 to A)
(S1 to B)
C
Output
thru 9
L
V
V
DD
out
C
L
C
Source Drive
L
V
(S1 to B)
Clock to
out
Output
desired
outputs
S1 to A
− V
C
− V
L
DD
DD
C
L