MB86391 Fujitsu Microelectronics, Inc., MB86391 Datasheet
MB86391
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MB86391 Summary of contents
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... MPEG2 1chip Audio/Video Encoder MB86391 Product Specification Copyright © FUJITSU LIMITED ALL RIGHTS RESERVED MB86391 Product Specification Rev. 1.1 Revision 1.1 12, November 2001 12, November 2001 ...
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... K Use of product in any manner that complies with the MPEG-2 standard is expressly prohibited without a license under applicable patents in the MPEG-2 patent portfolio, which license is available from MPEG LA, L.L.C., 250 steele street, suite 300, Denver, Colorado, USA 80206 MB86391 Product Specification Rev. 1.1 FUJITSU LIMITED ...
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... Bit Stream Output Port.................................................................................................155 2.3.8 Test Signals...............................................................................................................166 3 Functional Description....................................................................................................................177 3.1 Host/SDRAM Interface............................................................................................................177 3.1.1 Access by External Master...........................................................................................188 3.1.1.1 MB86391 Internal Resource Accessing..............................................................188 3.1.1.2 SDRAM Accessing........................................................................................... 20 3.1.1.3 External Resource Accessing...........................................................................244 3.1.2 Internal Controller Master Accessing .............................................................................266 3.1.2.1 External Resource Accessing...........................................................................266 3.1.2.2 External Boot ROM Read.................................................................................288 3 ...
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... Overall Control ............................................................................................................ 47 4.4.1.1 Clock Input...................................................................................................... 47 4.4.1.2 Reset Input ..................................................................................................... 48 4.4.2 Host/SDRAM Interface................................................................................................. 49 4.4.2.1 Host Interface.................................................................................................. 49 4.4.2.2 SDRAM Interface Signals ................................................................................. 52 4.4.3 Serial Interface............................................................................................................ 54 4.4.4 SDRAM Interface for Video Encoding............................................................................. 56 4.4.5 Video Input Interface.................................................................................................... 58 4.4.6 Audio Input Interface.................................................................................................... 59 4.4.7 Bit Stream Output Port.................................................................................................. 63 MB86391 Product Specification Rev. 1.1 FUJITSU LIMITED Proprietary and Confidential 12, November 2001 ...
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... Product Overview The MB86391 (MPEG2 1chip Audio/Video Encoder LSI that accomplishes all of video encoding, audio encoding, and video and audio encode stream data multiplexing with a single chip rather than several LSIs as in the past. This LSI enables you to minimize the size, cost and power consumption of MPEG2 application systems, such as digital video recorders ...
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... System Configuration Fig. 1.2 shows an example system configuration using the MB86391. System Controller Bus Switch External boot ROM Fig. 1.2 : System configuration (Example)) MB86391 Product Specification Rev. 1.1 Serial interface XMBREQ, XBREQ XBGRNT D31:0, ADRS27 :26, 17:2, control XBUSEN, BUSDIR, XBGRNT MPEG2 SDRAM control Decoder Bit stream output port ...
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... External SDRAM I/F for memory video encoding interface Host/SDRAM I/F Serial interface Time base corrector MB86391 Product Specification Rev. 1.1 Table 1.3.1 : Major items Table 1.3.2 : Function list Compliant to ISO/IEC13818 2 (MPEG2 video)MP@ML and ISO/IEC11172 2 (MPEG1 video) When interlacing at 29.97Hz Compatible with size 32m 32n less than 720 480 ( any integers) ...
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... Package MB86391 Product Specification Rev. 1.1 Proprietary and Confidential 12, November 2001 4 FUJITSU LIMITED ...
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... The TBC (Time Base Corrector) function is accomplished by buffering video data in the SDRAM. Arbitrates SDRAM and MB86391 internal register access requests from MB86391 internal blocks and external master devices. Also used as the command interface with the host. Downloads dedicated firmware to the external SDRAM via this interface at the time of serial booting ...
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... SDADRS11:0 32 SDDATA31:0 SDDQM XSDWE XSDCAS XSDRAS 2 XSDCS 16 SDCKE 32 SDCLK 2 VCLK XVSYNC XHSYNC 2 FIELD XVALID MB86391 8 DVIDEO7:0 ASCLK ALRCK ACLK ADATA STCLK STREQ STEN 8 STDATA7:0 TSPSSYNC 47 Power/GND 3 Test signals Total external pin count :208 Fig. 2.1 : I/O signal diagram 6 FUJITSU LIMITED Proprietary and Confidential ...
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... ALRCK 203 ACLK 204 STREQ 205 INDEX XTST 206 VDDE 207 208 Fig. 2.2.1 : Pin arrangement diagram MB86391 Product Specification Rev. 1.1 MB86391 HQFP208(FPT-208P-M04) 7 FUJITSU LIMITED Proprietary and Confidential 104 ADRS8 103 ADRS7 102 ADRS6 101 ADRS5 100 VDDE ...
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... VDDI 101 50 I/O D26 102 51 I/O D27 103 52 I/O D28 104 VDDE : 3.3V power supply, VDDI : 1.8V power supply, AVDD : 1.8V power supply to PLL VSS, AVSS : ground MB86391 Product Specification Rev. 1.1 Table 2.2.2 : Pin number list I/O Pin name Pin No. I/O Pin name I/O D29 105 I/O ADRS9 I/O D30 106 I/O ADRS10 ...
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... Clock Select Main Clock 26 MCLKI Input 33 XRESET Reset 27 PLLTHR PLL through MB86391 Product Specification Rev. 1.1 Table 2.3.1 : Overall control pins Pull up Bit I/O Active /down Internal controller operating frequency selection input pin. When the screen size D1, select 54MHz operations. ‘H’ = 54MHz operations ‘ ...
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... Column 94 XSPCAS Address Strobe Row 93 XSPRAS Address Strobe Clock 98 SPCKE Enable SDRAM 97 SPSDCLK Clock MB86391 Product Specification Rev. 1.1 Pull Bit I/O Active up/down Host/SDRAM interface bus clock 1 O (27MHz) output pin Address (upper 2bits) I/O pins 2 I/O Address (lower 16bits) I/O pins 16 I/O 32bit data I/O pins 32 I/O Interrupt request input pins ...
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... Pin symbol Pin name 19 SCLK Serial Clock Serial Data 18 SDATAIN Input Serial Data 17 SDATAOUT Output MB86391 Product Specification Rev. 1.1 Table 2.3.3: Serial interface pins Pull Bit I/O Active up/down Serial I/F serial clock input pin Serial I/F data input pin Serial I/F data output pin. ...
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... Address Strobe 179 XSDCS Chip Select Clock 180 SDCKE Enable SDRAM 181 SDCLK Clock MB86391 Product Specification Rev. 1.1 Pull Bit I/O Active up/down Address output (12bits) pins to SDRAM 12 O connected to the video encoding SDRAM interface Data I/O (32bits) pins to SDRAM connected to the video encoding SDRAM ...
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... XVSYNC Sync Horizontal 131 XHSYNC Sync 129 FIELD Field 128 XVALID Data Valid Digital 126 to 119 DVIDEO7:0 Video MB86391 Product Specification Rev. 1.1 Pull Bit I/O Active up/down Video clock input pin Vertical sync input pin Horizontal sync input pin Field ID input pin ...
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... ALRCK Clock Audio Bit 204 ACLK Clock Audio Serial 200 ADATA Data MB86391 Product Specification Rev. 1.1 Pull Bit I/O Active up/down System clock input pin for audio. Input 1 I clock 256 times the audio sampling frequency. Must be in sync with MCLKI. ...
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... Bit Stream 3 STEN Output Enable Bit Stream STDATA7:0 Data7:0 2 TSPSSYNC TS/PS Sync MB86391 Product Specification Rev. 1.1 Pull Bit I/O Active up/down Bit stream transfer clock input pin. The 1 I pullup clock is for stream reading in transfer clock sync mode. Bit stream transfer request input pin. ...
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... Test Signals Pin No. Pin symbol Pin name 201 VPDX 202 TESTMODE 206 XTST MB86391 Product Specification Rev. 1.1 Table 2.3.8: Test pins Pull Bit I/O Active up/down A test pin. For typical usage, connect VSS. A test pin. For typical usage, connect pull down OPEN or VSS ...
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... Install the MB86391 and the SDRAM as physically close as possible. Pull up the SPSDCLK signal line with a resistance of 200 The SPSDCLK signal line must pattern of a single stroke, from the MB86391, the sending end, through the SDRAM CLK to the point of connection to the pull up resistance. ...
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... The external master outputs valid data to XRDWR, ADRS27:26, 17:2 and D31:0 and asserts the XAS signal. Note that XBREQ must be asserted up to this cycle. (4) The MB86391 fetches the address and control signal statuses in (3) and then negates XBGRNT. At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26,17 ...
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... Hi Z. (5) The MB86391 sets BUSDIR to ’H’ (read direction) to allow read data output. (6) The MB86391 outputs valid data to D31:0 at the same time as it asserts XREADY (the external master fetches read data at this timing). (7) The MB86391 negates XBUSEN and resets to its normal state. ...
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... Hi Z. (5) The MB86391 re outputs the address fetched in (4) to the SDRAM at the command. (6) The MB86391 asserts the XREADY signal during the cycle to write data to the SDRAM and notifies it to the external master. (7) The MB86391 negates XBUSEN, sets BUSDIR to 'H' (read direction), and resets to normal state. ...
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... The MB86391 re outputs the address fetched in (4) to the SDRAM at the command. (6) The MB86391 sets BUSDIR to ’H’ (read direction) to allow read data output. (7) The MB86391 asserts the XREADY signal during the SDRAM data read cycle and notifies it to the external master. ...
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... Hi Z. (5) The MB86391 re outputs the address fetched in (4) to the SDRAM at the command. (6) The MB86391 asserts the XREADY signal during the cycle to write data to the SDRAM and notifies it to the external master. (7) The MB86391 negates XBUSEN, sets BUSDIR to 'H' (read direction), and resets to normal state. ...
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... The MB86391 re outputs the address fetched in (4) to the SDRAM at the command. (6) The MB86391 sets BUSDIR to ’H’ (read direction) to allow SDRAM read data output. (7) The MB86391 asserts the XREADY signal during the SDRAM data read cycle and notifies it to the external master. ...
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... XAS, XRDWR, and ADRS27:26, 17:2 fetched in (4) to the external resource. (6) The external resource asserts the XREADY signal and notifies that data write is complete. (7) The MB86391 negates XBUSEN and XREADY, sets BUSDIR to ‘H’ (read direction) and resets to its normal state. Notes: After negating XREADY, the next request for bus privilege (asserting XBREQ) is allowed ...
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... XAS, XRDWR, and ADRS27:26,17:2 fetched in (4) to the external resource. (6) The external resource asserts the XREADY signal and notifies that valid data is output to D31:0. (7) The MB86391 negates XBUSEN and XREADY, sets BUSDIR to 'H' (read direction), and resets to normal state. Notes: After negating XREADY, the next request for bus privilege (asserting XBREQ) is allowed. The external resource needs to be set after setting XREADY to 'H." ...
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... With XCSn (n = 5,4) asserted, the controller selects an external resource and, in conjunction with XAS assertion, outputs valid data to XRDWR, ADRS27:26, 17:2 and D31:0. (3) When the external resource asserts the XREADY signal, the MB86391 negates XCSn (n = 5,4) and sets XRDWR to ’H’ (read, normal state) at the same time as the selection is cancelled (4) The controller negates the XBUSEN and XREADY signals to reset to its normal state ...
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... All ‘ H’ XBUSEN(O) BUSDIR(O) Fig. 3.1.2.1b: External resource access timing (Read) (1) The MB86391 sets BUSDIR to 'L' (read direction) and XREADY and asserts XBUSEN to prepare for accessing. (2) With XCSn (n = 5,4) asserted, the MB86391 selects an external resource and, in conjunction with XAS, outputs valid data to ADRS27:26, 17:2. ...
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... BUSDIR(O) Fig. 3.1.2.2: External boot ROM access timing (Read) (1) With XCS0 asserted, the MB86391 selects the external boot ROM, sets BUSDIR to 'L' (read direction) and XREADY and asserts XBUSEN to prepare for accessing. (2) In conjunction with XAS, the MB86391 outputs valid data to ADRS27:26, 17:2 (let the external boot ROM output read data to the data bus after confirming XCS0) ...
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... Host Interrupt Output (XEXTIRPT) This is the interrupt output from the internal controller to the external host. The firmware dedicated to the internal controller notifies the external host of the end of command processing, for example. (For more information, see "MB86391 Control Protocol Command Specification (Parallel I/F)"). MB86391 Product Specification Rev ...
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... Address Map Table 3.1.4: MB86391 address map *1 Address 0x0000000 to 0x0000FFF 0x0001000 to 0x003FFFF 0x4000000 to 0x401FFFF 0x4020000 to 0x403FFFF 0x8000000 to 0x87FFFFF 0xC000000 to 0xC00FFFF 0xC010000 to 0xC01FFFF 0xC020000 to 0xC02FFFF 0xC100000 to 0xC10FFFF 0xC200000 to 0xC20FFFF 0xC300000 to 0xC30FFFF 0xC400000 to 0xC40FFFF 0xC800000 to 0xC80FFFF *1: Any space with no description is reserved. *2: An area of 4 Mbytes is actually used. ...
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... StartBit falling edge of the SDATAIN signal regardless of SCLK. Use even parity from FM1 through DataN. After the parity bit needed as StopBit. However received at this point recognized as a break signal and invalidates receive data. MB86391 Product Specification Rev. 1.1 Data section ...
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... When using start stop synchronization mode, pull the SDATAOUT pin down with about 3.3k . When using SCLK synchronization mode, pull the SDATAOUT pin up with about 3. not possible to change the transport mode during working. Use even parity from FM1 through DataN. MB86391 Product Specification Rev. 1.1 Data section ...
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... Note: Install the MB86391 and the SDRAM as physically close as possible. Pull up the SDCLK signal line with a resistance of 200 SDCLK signal line must pattern of a single stroke, from the MB86391, the sending end, through the SDRAM CLK to the point of connection to the pull up resistance. ...
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... Video Input Interface The video input interface is a dedicated interface between the MB86391 and an external device (such a an NTSC decoder) connected to the MB86391. Fig. 3.4 shows an example connection. NTSC decoder (SAA7113) VDO7:0 LCC RTS0 RTS1 Fig. 3.4: Example video input interface connection MB86391 Product Specification Rev ...
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... SAV/EAV signal in the D1 data. (b) Y/C multiplex input mode Input video data multiplexed in 4:2:2 format (CbYCr in that order) to DVIDEO7:0 pin as well as sync and valid pixel signals to the XVSYNC, XHSYNC, FIELD and XVALID pins. MB86391 Product Specification Rev. 1.1 Proprietary and Confidential ...
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... Audio Input Interface The audio input interface is a dedicated audio data interface between the MB86391 and the audio A/D converter connected to the MB86391. Fig. 3.5 shows an example connection. Audio 27MHz oscillation Note: MCLKI must be in sync with ASCLK. Fig. 3.5: Example audio input interface connection (Master mode) ...
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... Master/Slave Mode Master (the MB86391 outputs ACLK and ALRCK) and slave (input of ACLK and ALRCK from the audio A/D converter to the MB86391) modes can be switched. 3.5.2 Input Formats Setting each of the following parameters allows compatibility with various input formats: (1) MSB first/LSB first of data (2) Packing ALRCK with data (left/right packing)) (3) ALRCK polarity (‘ ...
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... Fig. 3.6a: 27 MHz sync mode timings (1) When ready to receive streams, set STREQ to 'H.' (2) When valid data exists, the MB86391 sets STEN to ’H’ at STDATA to instruct data fetching. It also sets the TSPSSYNC signal simultaneously to 'H' at the sync byte "0x47" if the stream is TS, and at pack start code "0x000001BA" the leading byte of the program end code " ...
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... Fig. 3.6c: External clock mode (CBR) (1) Input the transfer clock to STCLK according to the bit and set STREQ to 'H.' (2) While transferring, the MB86391 outputs 'H' to STEN at all times and outputs valid data according to the external clock STCLK. It also simultaneously sets the TSPSSYNC signal to 'H' at the sync byte " ...
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... Input the transfer clock to STCLK according to the bit and set STREQ to 'H.' (2) While transferring, the MB86391 outputs 'H' to STEN at all times and outputs valid data according to the external clock STCLK. It also simultaneously sets the TSPSSYNC signal to 'H' at the sync byte "0x47" if the stream is TS, and at the pack start code "0x000001BA" the leading byte of the program end code " ...
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... Error Notification Function The MB86391 has a built in function to notify outside of an error when it occurs. In case of an error, it sets the XERROR pin to 'L' to output error information from the bit stream output port. When the error information is output, the STEN and TSPSSYNC pins are set to 'L' (Fig.3.7). Tables 3.7a and 3.7b list the pins and error descriptions related to occurrence of errors ...
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... Boot Operations The MB86391 starts booting operations when the internal controller starts the boot program of the internal ROM. The program required for the operation is downloaded to the SDRAM interface connected to the host/SDRAM according to the processing flow in Fig. 3.8. Each downloading procedure is described in the next and subsequent chapters ...
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... Table 3.8.3) from the host/SDRAM interface to the SDRAM by directly accessing the memory. During this period, the internal ROM boot program of the MB86391 infinite loop waiting for interruption. Therefore, from the host/SDRAM interface, instruct to start the program by executing parallel API interruption (by writing to the register) after direct downloading to the SDRAM is complete ...
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... Item *1 Supply voltage Input voltage Output voltage Output current Operating temperature Storage temperature *1: VDDI – Internal logic power supply, VDDE – External I/O power supply, AVDD PLL power supply MB86391 Product Specification Rev. 1.1 Table 4.1: Maximum ratings Symbol Max. ratings VDDI 0.5 to 2.5 VDDE 0.5 to 4.0 AVDD ...
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... Otherwise, you might destroy the device. After turning on the power, keep the PLLTHR pin set to the L level for more than 2 s. Next, set the PLLTHR pin to the H level and then input the L level to the XRESET signal for more than 300 s. MB86391 Product Specification Rev. 1.1 Ratings Symbol Min ...
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... Input leakage current Pull up/down resistance Pin capacity *1: Condition IOH= 100 A *2: Condition IOL=100 A *3: Condition VOH=VDDE 0.4V *4: Condition VOL=0.4V *5: BCLK, SPSDCLK, and SDCLK signal output characteristics *6: Output characteristics of signals other than those in *5 MB86391 Product Specification Rev. 1.1 Ratings Symbol Min. Typical VOH VDDE 0.2 VOL 0 ...
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... AC Characteristics 4.4.1 Overall Control 4.4.1.1 Clock Input MCLKI Item MCLKI frequency MCLKI H duration MCLKI L duration MB86391 Product Specification Rev. 1.1 1/f MCLKI t t HMCLKI LMCLKI Symbol Condition f MCLKI t HMCLKI t LMCLKI 47 FUJITSU LIMITED Proprietary and Confidential Standard Unit Min. Typical Max. 27 MHz 12, November 2001 ...
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... Reset Input (a) After turning the power on PLLTHR XRESET Item PLLTHR L duration XRESET L duration (b) Other than after turning the power on XRESET Item XRESET L duration MB86391 Product Specification Rev. 1.1 t LPLLTHR t LRESET Symbol Condition Min LPLLTHR t 300 LRESET t LRST Symbol Condition Min. t 500 ...
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... Host/SDRAM Interface 4.4.2.1 Host Interface Clock (BCLK) BCLK Item BCLK frequency BCLK H duration BCLK L duration MB86391 Product Specification Rev. 1.1 1/f BCLK t t HBCLK LBCLK Symbol Condition f BCLK t HBCLK t LBCLK 49 FUJITSU LIMITED Proprietary and Confidential Standard Unit Min. Typical Max. 27 MHz 12, November 2001 ...
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... Input sigals BCLK ADRS, D, IRQ, XAS, XRDWR, XBMREQ, XBREQ, XREADY Output signals BCLK ADRS, D, XAS, XRDWR, XCS, XBGRNT, XBUSEN, BUSDIR, XREADY, XEXTIRPT, XERROR MB86391 Product Specification Rev. 1.1 Proprietary and Confidential IADRSS, IDS, IRQS , IASS, IRWS, IADRSH, IDH ...
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... XAS output delay time XCS delay time XREADY input setup time XREADY input hold time XREADY output delay time XBUSEN delay time BUSDIR delay time XEXTIRPT delay time XERROR delay time MB86391 Product Specification Rev. 1.1 Proprietary and Confidential Standard Symbol Condition Min. Typical ...
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... SDRAM Interface Signals Clock (SPSDCLK) SPSDCLK Item SPSDCLK frequency SPSDCLK H duration SPSDCLK L duration Input signals SPSDCLK D31:0 Output signals SPSDCLK D31:0, ADRS14:2, XSPWE, XSPCAS, XSPRAS, SPCKE MB86391 Product Specification Rev. 1.1 1/f SPSDCLK t t HSPSDCLK LSPSDCLK Symbol Condition Min. f SPSDCLK t HSPSDCLK t LSPSDCLK t t RDS ...
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... Item Address output delay time Read data setup time Read data hold time Data output delay time SPWE delay time SPCAS delay time SPRAS delay time SPCKE delay time MB86391 Product Specification Rev. 1.1 Proprietary and Confidential Standard Symbol Condition Min. Typical ...
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... Serial Interface Clock (SCLK) SCLK Item SCLK frequency SCLK H duration SCLK L duration Input signals SCLK SDATAIN Output signals SCLK SDATAOUT MB86391 Product Specification Rev. 1.1 1/f SCLK t t HSCLK LSCLK Symbol Condition f SCLK t HSCLK t LSCLK t t SDIS SDIH t SDOD 54 FUJITSU LIMITED Proprietary and Confidential ...
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... Item Serial data input setup time Serial data input hold time Serial data output delay time MB86391 Product Specification Rev. 1.1 Proprietary and Confidential Standard Symbol Condition Min. Typical t 100 SDIS t 100 SDIH t SDOD 12, November 2001 55 FUJITSU LIMITED Unit Max 160 ...
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... SDRAM Interface for Video Encoding Clock (SDCLK) SDCLK Item SDCLK frequency SDCLK H duration SDCLK L duration Input signals SDCLK SDDATA31:0 Output signals SDCLK SDDATA31:0, SDADRS11:0, SDDQM, XSDWE, XSDCAS, XSDRAS, XSDCS, SDCKE MB86391 Product Specification Rev. 1.1 1/f SDCLK t t HSDCLK LSDCLK Symbol Condition f SDCLK t HSDCLK t LSDCLK ...
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... Read data setup time Read data hold time Data output delay time XSDDQM delay time XSDWE delay time XSDCAS delay time XSDRAS delay time XSDCS delay time XSDCKE delay time MB86391 Product Specification Rev. 1.1 Proprietary and Confidential Standard Symbol Condition Min. Typical t 3 ...
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... Item XVSYNC setup time XVSYNC hold time XHSYNC setup time XHSYNC hold time FIELD setup time FIELD hold time XVALID setup time XVALID hold time DVIDEO setup time DVIDEO hold time MB86391 Product Specification Rev. 1.1 1/f VCLK t t HVCLK LVCLK Symbol Condition ...
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... ASCLK H duration ASCLK L duration Note: fs: Audio sampling frequency Audio bit clock output (ACLK) ASCLK t ACLKD ACLK Item ACLK frequency ACLK H duration ACLK L duration ACLK delay time Note: fs: Audio sampling frequency MB86391 Product Specification Rev. 1.1 t ASCLK t t HASCLK LASCLK Symbol Condition t ASCLK t ...
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... Serial audio data input signals ACLK ADATA Audio sampling clock output signals ASCLK ALRCK Item ADATA setup time ADATA hold time ALRCK cycle time ALRCK delay time MB86391 Product Specification Rev. 1 ADS ADH t ALRCKD t ALRCKO Symbol Condition Min ADS ...
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... Audio bit clock input (ACLK) ACLK Item ACLK cycle duration ACLK H duration ACLK L duration Note: fs: Audio sampling frequency Serial audio data input signals ACLK ADATA Audio sampling clock input signals ACLK ALRCK MB86391 Product Specification Rev. 1.1 t ACLKI t t HACLKI LACLKI Symbol Condition t ACLKI ...
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... Item ADATA setup time ADATA hold time ALRCK cycle time ALRCK setup time ALRCK hold time MB86391 Product Specification Rev. 1.1 Proprietary and Confidential Standard Symbol Condition Min. Typical t 50 ADS t 50 ADH t 20 ALRCKI t 50 ALRCKS t 50 ALRCKH 12, November 2001 62 FUJITSU LIMITED Unit Max ...
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... MHz sync/handshake mode Input singnals BCLK STREQ Output signals BCLK STEN, STDATA, TSPSSYNC Item STREQ setup time STREQ hold time STEN delay time STDATA delay time TSPSSYNC delay time MB86391 Product Specification Rev. 1.1 Proprietary and Confidential t t BSTRQS BSTRQH t t BSTED, BSTDTD, t BTPSYNCD ...
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... Transfer clock sync mode Clock (STCLK) STCLK Item STCLK cycle duration STCLK H duration STCLK L duration Input signals STCLK STREQ Output signals STCLK STEN, STDATA, TSPSSYNC MB86391 Product Specification Rev. 1.1 t STCLK t t HSTCLK LSTCLK Symbol Condition t STCLK t HSTCLK t LSTCLK t t STRQS STRQH ...
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... Item STREQ setup time STREQ hold time STEN delay time STDATA delay time TSPSSYNC delay time MB86391 Product Specification Rev. 1.1 Proprietary and Confidential Standard Symbol Condition Min. Typical t 0 STRQS t 60 STRQH t STED t STDTD t TPSYNCD 12, November 2001 65 FUJITSU LIMITED Unit Max. ...