MB15U10 Fujitsu Microelectronics, Inc., MB15U10 Datasheet - Page 7

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MB15U10

Manufacturer Part Number
MB15U10
Description
Dual Serial Input Pll Frequency Synthesizer On-chip 1.1 Ghz Prescaler
Manufacturer
Fujitsu Microelectronics, Inc.
Datasheet

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Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider, program-
mable divider (PLL1) and programmable divider (PLL2) separately by means of address setting.
Binary serial data is entered via the Data pin.
One bit of data is shifted into the internal shift register on the rising edge of the clock. When the load enable pin is high, stored
data is latched.
a) Serial data input format
Note: Start data input with MSB first.
FUNCTIONAL DESCRIPTIONS
16
16
M
X
A
M
1
0
B
MA0 to 16 : Divide ratio setting bits of the main counter (PLL1)
MB0 to 16 : Divide ratio setting bits of the main counter (PLL2)
R0 to 11
SR
P0 to 3
OLA, B
CR1, 2
PS1, 2
TS
X
0
15
15
M
(MSB)
X
A
M
2
0
B
14
M
14
X
A
3
0
M
B
: Divide ratio setting bits of the reference counter
: Divide ratio select bit of reference frequency (PLL1 and PLL2)
: Setting bits of P0 to P3 output pins
: Select bits of P0/LD pin output
: Select bits of charge pump output current
: Power saving mode control bits
: Test bits (Set ”0” at ordinary use.)
: Dummy bits (Set ”0” or ”1”.)
: Set ”0”
13
M
13
P
A
S
4
0
T
M
B
12
12
O
M
A
A
S
R
M
5
L
B
Auxiliary bit for test (no need at ordinary use)
11
11
M
11
O
R
6
L
B
A
M
B
10
10
M
10
C
R
R
7
1
A
M
B
C
R
M
R
A
M
8
2
9
9
B
9
Data setting
M
X
A
R
9
8
8
M
B
8
10
M
X
A
R
M
7
7
B
7
11
M
P
S
A
R
1
6
6
M
B
6
Direction of data input
12
M
P
S
A
R
2
5
5
M
B
5
13
M
P
A
R
M
3
4
4
B
4
14
M
P
A
R
M
2
3
3
B
3
15
M
P
A
R
1
2
2
M
B
2
16
M
X
A
R
1
1
M
B
1
17
M
X
A
R
M
0
0
B
0
[ See Table 1 ]
[ See Table 2 ]
[ See Table 3 ]
[ See Table 4 ]
[ See Table 5 ]
[ See Table 6 ]
[ See Table 7 ]
[ See Table 8 ]
[ See Table 9 ]
18
0
0
0
0
0
19
0
1
1
1
0
MB15U10
Address
(LSB)
20
0
0
0
1
0
21
1
0
1
0
0
7

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