AD684 Analog Devices, AD684 Datasheet
AD684
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AD684 Summary of contents
Page 1
... Each SHA channel can acquire a signal in less than 1 s and retain the held value with a droop rate of less than 0. Excellent linearity and ac performance make the AD684 an ideal front end for high speed 12- and 14-bit ADCs. The AD684 has a self-correcting architecture that minimizes hold mode errors and insures accuracy over temperature ...
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... Cerdip (Q) NOTES 1 Specified and tested over an input range Maximum current the AD684 can source (or sink). Testing guarantees that the accuracy of the held signal remains within 2 its initial value. 3 The output is protected for a short circuit to common and V at nominal voltage levels ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD684 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... AD684–Typical Characteristics Interchannel Isolation vs. Frequency Effective Aperture Delay vs. Frequency Supply Current vs. Supply Voltage Power Supply Rejection Ratio vs. Frequency Bias Current vs. Input Voltage Acquisition Time (to 0.01 %) vs. Input Step Size –4– Droop Rate vs. Temperature Supply Current vs. Temperature REV. A ...
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... Both inputs and outputs are treated as single ended signals, referred to common. The AD684 utilizes a proprietary circuit design which includes a self-correcting architecture. This sample-and-hold circuit corrects for internal errors after the hold command has been given, by compensating for amplifier gain and offset errors, and charge injection errors ...
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... The nominal hold mode offset is specified for input condition. Over the input range of – the AD684 is also characterized for an effective gain error and nonlinearity of the held value, as shown in Figure 3. As indicated by the AD684 specifications, the hold mode offset is very well matched between channels and stable over temperature ...
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... Figure 5. Figure 5. RMS Noise vs. Input Bandwidth of ADC DRIVING THE ANALOG INPUTS For best performance important to drive the AD684 analog inputs from a low impedance signal source. This enhances the sampling accuracy by minimizing the analog and digital crosstalk ...
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... AD684 and the high speed 12-bit A-to-D converter, the AD7672. Four input signals are simultaneously sampled by the AD684 as the HOLD command is given. One of the four held Figure 9. Data Acquisition System Using the AD684 and the AD7672 outputs is selected by the ADG201, quad CMOS switch, and buffered by the AD711. The AD588 provides the reference voltage with switches A-B and C-D selecting a – ...