ISL96017 Intersil Corporation, ISL96017 Datasheet - Page 4

• Manufacturer Part Number: ISL96017
• Description: 128-Tap DCP / 16kbit EEPROM and I2C Serial Interface
• Manufacturer: Intersil Corporation

Electrical Specifications
DCP IN RESISTOR MODE (Measurements between RH and RW with RL not connected)
EEPROM SPECS
SERIAL INTERFACE SPECS
R
t
WC
(Note 11,13)
(Note 8,10)
127
Hysteresis
(Note 8,9)
SYMBOL
t
t
t
t
t
HD:DAT
SU:STO
SU:STA
HD:STA
SU:DAT
RDNL
t
RINL
t
(Note 12) Non-Volatile Write Cycle Time
t
TC
Cpin
f
HIGH
V
LOW
V
SCL
t
BUF
V
(Note 8) Resistance Offset.
t
AA
IN
OL
IH
IL
R
Resistance Temperature Coefficient
Resistance Differential Non-
Linearity
Resistance Integral Non-Linearity
EEPROM Endurance
EEPROM Retention
WP, SDA, and SCL Input Buffer
LOW Voltage
WP, SDA and SCL Input Buffer
HIGH Voltage
SDA and SCL Input Buffer
Hysteresis
SDA Output Buffer LOW Voltage,
Sinking 4mA
WP, SDA, and SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs.
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup Time
PARAMETER
4
Over recommended operating conditions unless otherwise stated. All voltages with respect to GND. (Continued)
U version - DCP Register set to 7F hex.
Measured between R
W version - DCP Register set to 7F hex.
Measured between R
At 55°C
Any pulse narrower than the max spec is
suppressed
SCL falling edge crossing 30% of VDD, until
SDA exits the 30% to 70% of VDD window
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VDD during
the following START condition
Measured at the 30% of VDD crossing
Measured at the 70% of VDD crossing
SCL rising edge to SDA falling edge. Both
crossing 70% of VDD
From SDA falling edge crossing 30% of VDD to
SCL falling edge crossing 70% of VDD
From SDA exiting the 30% to 70% of VDD
window, to SCL rising edge crossing 30% of
VDD
From SCL rising edge crossing 70% of VDD to
SDA entering the 30% to 70% of VDD window
From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VDD
ISL96017
TEST CONDITIONS
H
H
and R
and R
W
W
pins.
pins.
1,000,000
-0.75
0.05*
1300
1300
VDD
VDD
MIN
0.7*
-0.3
600
600
600
100
600
50
-1
0
0
0
(Note 1)
±100
TYP
0.5
1
6
MAX
VDD
VDD
0.75
+0.3
0.3*
400
900
0.4
12
10
50
2
5
1
April 17, 2006
(Note 1)
(Note 1)
ppm/°C
Cycles
Years
UNIT
FN8243.1
kHz
ms
MI
MI
MI
MI
pF
ns
ns
ns
ns
ns
ns
ns
ns
V
V
V
ns
ns
V