ISL90841 Intersil Corporation, ISL90841 Datasheet
ISL90841
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ISL90841 Summary of contents
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... Data Sheet 2 ® Low Noise, Low Power I C The ISL90841 integrates four digitally controlled potentiometers (XDCP monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the ...
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... SCL 4 SDA 5 GND 6 RW2 7 RH2 8 RW1 9 RH1 VCC 13 RH0 14 RW0 2 ISL90841 V CC WR3 DCP3 WR2 DCP2 POWER-UP, INTERFACE, CONTROL AND STATUS LOGIC WR1 DCP1 WR0 DCP0 GND DESCRIPTION “High” terminal of DCP3 “Wiper” terminal of DCP3 interface clock 2 ...
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... Differential non-linearity (Note 11) Roffset Offset (Note 10) R DCP to DCP matching MATCH (Note 13) TC Resistance temperature coefficient R (Note 14) 3 ISL90841 Recommended Operating Conditions Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85° 2.7V to 5.5V CC +0.3 Power rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW CC Wiper current of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA CC TEST CONDITIONS W option U option V = 3.3V @ 25° ...
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... STOP condition hold time for read, or HD:STO volatile only write t Output data hold time DH (Note 15) t SDA and SCL rise time R (Note 15) 4 ISL90841 TEST CONDITIONS 400kHz; SDA = Open; (for I C, active, SCL read and write states +5.5V interface in standby state ...
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... TIMING) SDA (OUTPUT TIMING) A0 and A1 Pin Timing START SCL SDA IN A0 ISL90841 TEST CONDITIONS From 70 Total on-chip and off-chip Maximum is determined For Cb = 400pF, max is about 2~2.5kΩ For Cb = 40pF, max is about 15~20kΩ Before START condition ...
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... T=+25° 100 150 TAP POSITION (DECIMAL) FIGURE 1. WIPER RESISTANCE vs TAP POSITION [I FOR 50kΩ ( TOTAL 6 ISL90841 ) and V(R ) are V(R ) for the DCP register set to FF hex and 00 hex respectively. LSB is the 255 × ---------------- - for 240 decimal -40° ...
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... CC V =2.7, T=-40°C -0 =5.5, T=-40° 132 TAP POSITION (DECIMAL) FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 50kΩ (U) 7 ISL90841 (Continued) V =2.7, T=-40° =5.5, T=+85°C CC 200 250 FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER FIGURE 6. FSerror vs TEMPERATURE FOR 50kΩ (U) V =2.7, T=+25°C ...
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... TAP POSITION (DECIMAL) FIGURE 11. TC FOR RHEOSTAT MODE IN ppm SIGNAL AT WIPER (WIPER UNLOADED) WIPER MOVEMENT MID POINT FROM 80h TO 7fh FIGURE 13. MIDSCALE GLITCH, CODE 80h to 7Fh (WIPER 0) 8 ISL90841 (Continued FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm 182 232 ...
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... Protocol Conventions Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 15). On power-up of the ISL90841 the SDA pin is in the input mode. 9 ISL90841 ...
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... FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS SCL FROM MASTER SDA OUTPUT FROM TRANSMITTER SDA OUTPUT FROM RECEIVER START FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER SIGNALS FROM THE MASTER SIGNAL AT SDA SIGNALS FROM THE ISL90841 S SIGNALS T FROM THE A IDENTIFICATION MASTER R BYTE WITH T R/W=0 SIGNAL AT SDA ...
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... A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL90841 responds with an ACK. At this time, the device enters its standby state (See Figure 17). Read Operation A Read operation consist of a three byte instruction followed by one or more Data Bytes (See Figure 18) ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 ISL90841 14-Lead Plastic, TSSOP, Package Code V14 .025 (.65) BSC .169 (4.3) ...