ISL9000A Intersil Corporation, ISL9000A Datasheet - Page 8

• Manufacturer Part Number: ISL9000A
• Description: Dual LDO
• Manufacturer: Intersil Corporation

Pin Description
Typical Application
PIN #
10
1
2
3
4
5
6
7
8
9
VIN (2.3-6.5V)
ENABLE 1
ENABLE 2
NAME
CPOR
CBYP
POR1
POR2
GND
VO2
VO1
EN1
EN2
PIN
VIN
OFF
OFF
Open Drain Output (1mA)
Open Drain Output (1mA)
Low Voltage Compatible
Low Voltage Compatible
ON
ON
CMOS Input
CMOS Input
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
8
Ground
C1
TYPE
C1, C4, C5: 1µF X5R CERAMIC CAPACITOR
C2: 0.1µF X7R CERAMIC CAPACITOR
C3: 0.01µF X7R CERAMIC CAPACITOR
C2
C3
Supply Voltage/LDO Input:
Connect a 1μF capacitor to GND.
LDO-1 Enable.
LDO-2 Enable.
Reference Bypass Capacitor Pin:
Optionally connect capacitor of value 0.01μF to 1μF between this pin and GND to tune in the
desired noise and PSRR performance.
POR2 Delay Setting Capacitor Pin:
Connect a capacitor between this pin and GND to delay the POR2 output release after LDO-2
output reaches 94% of its specified voltage level. (200ms delay per 0.01μF).
GND is the connection to system ground. Connect to PCB Ground plane.
Open-drain POR Output for LDO-1 (active-low):
Internally connected to VO1 through 100kΩ resistor.
Open-drain POR Output for LDO-2 (active-low):
Internally connected to VO2 through 100kΩ resistor.
LDO-2 Output:
Connect capacitor of value 1μF to 10μF to GND (1μF recommended).
LDO-1 Output:
Connect capacitor of value 1μF to 10μF to GND (1μF recommended).
1
2
3
4
5
VIN
EN1
EN2
CBYP
CPOR
ISL9000A
ISL9000A
POR2
POR1
GND
VO1
VO2
10
9
8
7
6
C4
C5
DESCRIPTION
V
V
OUT2
OUT1
V
V
OUT2
OUT1
TOO LOW
TOO LOW
OK
OK
V
V
RESET 2
(200ms DELAY,
C3 = 0.01µF)
RESET 1
(2ms DELAY)
OUT1
OUT2
January 10, 2007
FN6391.0