ISL8724 Intersil Corporation, ISL8724 Datasheet - Page 5

• Manufacturer Part Number: ISL8724
• Description: (ISL8723 / ISL8724) Power Sequencing Controllers
• Manufacturer: Intersil Corporation

Electrical Specifications
ISL8723, ISL8724 Descriptions and
Operation
The ISL8723 and ISL8724 sequencers are quad voltage
sequencing controllers designed for use in multiple-voltage
systems requiring power sequencing of various supply
voltages. Individual voltage rails are gated on and off by
external N-Channel MOSFETs, the gates of which are
driven by an internal charge pump to ~V
a user programmed sequence.
With the ISL8723 the ENABLE must be asserted high and
all four voltages to be sequenced must be above their
respective user programmed Under Voltage Lock Out
(UVLO) levels before programmed output turn on
sequencing can begin. Sequencing and delay
determination is accomplished by the choice of external
cap values on the DLY_ON and DLY_OFF pins. The
SYSRST# goes high once all 4 UVLO inputs and ENABLE
are satisfied. Once all 4 UVLO inputs and ENABLE are
satisfied for 10ms, the four DLY_ON caps are
simultaneously charged with 1μA current sources to the
DLY_Vth level of 1.28V. As each DLY_ON pin reaches the
DLY_Vth level its associated GATE will then turn-on with a
10μA source current to the VQP voltage of VDD+5.6V.
Thus all four GATEs will sequentially turn on. Once at
DLY_Vth the DLY_ON pins will discharge to be ready when
next needed. After the entire turn on sequence has been
completed and all GATEs have reached the charge
pumped voltage (VQP), a 160ms delay is started to ensure
stability after which the RESET# output will be released to
go high. Subsequent to turn-on, if any input falls below its
UVLO point for longer than the glitch filter period, T
(~7μs) this is considered a fault. RESET#, SYSRST# and
all GATEs are simultaneously pulled low. In this mode the
SYSRST# Output Capacitance
SYSRST# Low to GATE Turn-off
SYSRST# High to GATE Turn-on
GATE
GATE Turn-On Current
GATE Turn-Off Current
GATE Current Range
GATE Pull-Down High Current
GATE High Voltage
GATE Low Voltage
BIAS
IC Supply Current
ISL8723 Stand By IC Supply Current
V
DD
Power On Reset
PARAMETER
5
V
DD
= 3.3V to +5V, T
DD
T
T
I
GATE_range
delSYS_G_1
delSYS_G_2
I
V
SYMBOL
Cout_srst
I
+5.6V (VQP) in
GATEoff_h
V
GATEoff_l
I
I
I
V
DD
GATEon
VDD_5V
VDD_sb
GATEh5
GATEl
_POR
A
FIL
ISL8723, ISL8724
= T
J
GATE = 80% of V
GATE = 50% of V
GATE = 0V
GATE = V
Within IC I
GATE = V
V
Gate Low Voltage, V
V
V
V
= -40°C to +85°C, Unless Otherwise Specified. (Continued)
DD
DD
DD
DD
= 5V
= 5V, Enabled and static
= 5V, ENABLE = 0V
rising
TEST CONDITIONS
DD
DD
GATE
, Disabled
, UVLO = 0V
GATEs are pulled low with ~75mA. Normal shutdown mode
is entered when no UVLO is violated and the ENABLE is
deasserted. When ENABLE is deasserted, RESET# is
asserted and pulled low. Next, all four shutdown ramp caps
on the DLY_OFF pins are charged with a 1μA source and
when any ramp-cap reaches DLY_Vth, a latch is set and a
10μA current is sunk on the respective GATE pin to turn off
its external MOSFET. When the falling GATE voltage is
approximately 1.5V, the GATE is pulled down the rest of the
way at a higher current level to ensure a hard turn-off. Each
individual external FET is thus turned off removing the
voltages from the load in the programmed sequence. The
SYSRST# will pull low concurrent with the last GATE being
pulled low.
The ISL8723 and ISL8724 have the same functionality
except for the complimentary ENABLE active polarity with
the ISL8724 having an ENABLE# input. Additionally the
ISL8723 also has a low power sleep state when disabled.
Upon bias the SYSRST# and RESET# pins are held low
before bias voltage = 1V.
The SYSRST# has both an input and output function. As an
output the SYSRST# pin is useful when implementing
multiple sequencers in a design needing simultaneous
shutdown as with a kill switch across all sequencers. Once
any UVLO is unsatisfied for longer than T
SYSRST# will pull low and pull all other SYSRST# pins low
that are on a common connection thus unconditionally
shutting down all outputs across multiple sequencers. As
an input, if it is pulled low all GATEs will be unconditionally
shut off and RESET# pulled low, see Figure 17. This pin
can also be used as a ‘no wait’ enabling input, if all inputs
(ENABLE and UVLO) are satisfied it does not wait through
max-min
DD
DD
+5V
+5V
DD
= 1V
V
DD
-12.5
MIN
8.3
+5.3V
-
-
-
-
-
-
-
-
-
V
DD
-10.2
TYP
10.2
0.27
0.01
0.4
0.6
2.2
10
40
75
30
+5.6V
FIL
MAX
12.5
0.31
2.41
-8.3
0.1
40
3
-
-
-
-
-
the related
December 21, 2006
UNIT
FN6413.0
mA
mA
ms
pF
μA
μA
μA
μA
ns
V
V
V