ISL6595 Intersil Corporation, ISL6595 Datasheet - Page 19

• Manufacturer Part Number: ISL6595
• Description: Digital Multiphase Controller
• Manufacturer: Intersil Corporation

an Acknowledge to indicate to the ISL6595 that the
transaction is not yet complete. The master again sends 8
clocks but does not drive the serial data line. The ISL6595
will respond with the LS-byte at the current address. The
master will respond with a Not Acknowledge to indicate to
the ISL6595 that the transaction is complete. The ISL6595
will stop driving the serial data line. The master then issues a
Stop condition to indicate that the transaction is complete.
I
Key Registers
Table 4 provides brief descriptions of several key configuration (R/W – read/write) and status (RO – read only) registers available
on the ISL6595 Digital Multiphase Controller.
isum_avg[18:0]
vavp_avg_mon[9:0]
kavp [9:0]
load_line_offset [4:0]
isum_max [7:0]
ptat_mon[5:0]
ptat_alert_ref[5:0]
ptat_shutdown_ref[5:0]
temp_mon[5:0]
therm_alert_ref[5:0]
therm_shutdown_ref[5:0] Thermistor shutdown temperature. Thermistor sensor
2
Data write
S et c urrent addres s
Read from c urrent addres s
C Read and Write Protocol
S
S
S
Driven by m as ter
sla ve _a d d r + W
sla ve _a d d r + W
REGISTER
sla ve _a d dr + R
VR load current. Averaged sum of all channel current data
over a user programmable averaging window
(default = 16ms).
AVP output voltage. Averaged VAVP monitored value ADC
voltage.
AVP loadline slope. Nominal value of load line slope
resistance.
AVP loadline VID offset. VID set-point load-line offset
tolerance voltage.
Overcurrent limit. Max load current threshold for over
current shutdown.
PTAT Temperature. Averaged PTAT calibration
temperature output.
PTAT alert temperature. PTAT sensor alert temperature
reference.
PTAT shutdown temperature. PTAT sensor shutdown
temperature reference.
Thermistor temperature. Averaged Thermistor monitor
temperature output.
Thermistor alert temperature. Thermistor sensor alert
temperature reference.
shutdown temperature reference.
A
A
A
19
re g_a d dr M S B
re g_a d dr M S B
re g_a d dr M S B
DESCRIPTION
A
A
A
TABLE 4. KEY REGISTERS
Driven by s lave
re g_a d dr LS B
re g_a d dr LS B
re g_a d dr LS B
ISL6595
If the ISL6595 has started an internal operation in response
to a transaction on the I
write, flash page erase) but the operation has not completed
before the last Acknowledge slot in the I
ISL6595 will add wait states by stretching the low portion of
the last clock cycle. This also occurs in response to
read/write requests to addresses that do not support
physical memory in the ISL6595. In this case, the ISL6595
will add wait states until an internal watchdog timer expires,
and the I
A
A
N
P
P
2
re g_d a ta M S B
FORMAT
C bus is guaranteed to be released.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
0.0mV
0.00A
0.0Ω
0.0V
0.0A
2
MIN
0°C
0°C
0°C
0°C
0°C
0°C
C bus (register read/write, flash
A
RANGE
3,196.875mV
re g_d a ta LS B
48.4375mV
524.288A
3.902mΩ
+204.0A
157.5°C
157.5°C
157.5°C
157.5°C
157.5°C
157.5°C
MAX
2
C bus protocol, the
RESOLUTION
0.003815mΩ
February 27, 2006
1.5625mV
3.125mV
0.800A
2.5°C
2.5°C
2.5°C
2.5°C
2.5°C
2.5°C
1mA
A
FN9192.0
P