ISL6568 Intersil Corporation, ISL6568 Datasheet - Page 10

• Manufacturer Part Number: ISL6568
• Description: Two-Phase Buck PWM Controller
• Manufacturer: Intersil Corporation

Interleaving
The switching of each channel in a multi-phase converter is
timed to be symmetrically out of phase with each of the other
channels. In a 3-phase converter, each channel switches 1/3
cycle after the previous channel and 1/3 cycle before the
following channel. As a result, the three-phase converter has
a combined ripple frequency three times greater than the
ripple frequency of any one phase. In addition, the peak-to-
peak amplitude of the combined inductor currents is reduced
in proportion to the number of phases (Equations 1 and 2).
Increased ripple frequency and lower ripple amplitude mean
that the designer can use less per-channel inductance and
lower total output capacitance for any performance
specification.
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3)
combine to form the AC ripple current and the DC load
current. The ripple component has three times the ripple
frequency of each individual channel current. Each PWM
pulse is terminated 1/3 of a cycle after the PWM pulse of the
previous phase. The peak-to-peak current for each phase is
about 7A, and the dc components of the inductor currents
combine to feed the load.
To understand the reduction of ripple current amplitude in the
multi-phase circuit, examine the equation representing an
individual channel peak-to-peak inductor current.
In Equation 1, V
voltages respectively, L is the single-channel inductor value,
and f
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
I
PP
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
=
S
(
----------------------------------------------------- -
is the switching frequency.
V
IN
PWM1, 5V/DIV
–
L f
V
IL1 + IL2 + IL3, 7A/DIV
FOR 3-PHASE CONVERTER
OUT
S
V
IN
IL1, 7A/DIV
IN
) V
and V
OUT
PWM3, 5V/DIV
OUT
10
1µs/DIV
are the input and output
IL3, 7A/DIV
PWM2, 5V/DIV
IL2, 7A/DIV
(EQ. 1)
ISL6568
ISL6568
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output-
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multi-phase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
The converter depicted in Figure 2 delivers 1.5V to a 36A load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has 11.9A
RMS input capacitor current. The single-phase converter
must use an input capacitor bank with twice the RMS current
capacity as the equivalent three-phase converter.
Figures 22 and 23 in the section entitled Input Capacitor
Selection can be used to determine the input-capacitor RMS
current based on load current, duty cycle, and the number of
channels. They are provided as aids in determining the
optimal input capacitor solution.
PWM Operation
The timing of each converter leg is set by the number of
active channels. The default channel setting for the ISL6568
is two. One switching cycle is defined as the time between
the internal PWM1 pulse termination signals. The pulse
termination signal is the internally generated clock signal
that triggers the falling edge of PWM1. The cycle time of the
I
C PP
,
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-
=
(
----------------------------------------------------------- -
V
INPUT-CAPACITOR CURRENT, 10A/DIV
IN
–
CAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
N V
L f
CHANNEL 1
INPUT CURRENT
10A/DIV
S
OUT
V
IN
CHANNEL 2
INPUT CURRENT
10A/DIV
) V
OUT
CHANNEL 3
INPUT CURRENT
10A/DIV
1µs/DIV
March 9, 2006
FN9187.4
(EQ. 2)