ISL6537A Intersil Corporation, ISL6537A Datasheet - Page 5

• Manufacturer Part Number: ISL6537A
• Description: ACPI Regulator/Controller
• Manufacturer: Intersil Corporation

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Electrical Specifications
Functional Pin Description
5VSBY (Pin 1)
5VSBY is the bias supply of the ISL6537A. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6537A enters a reduced
power mode and draws less than 1mA (I
5VSBY supply. The supply to 5VSBY should be locally
bypassed using a 0.1µF capacitor.
P12V (Pin 3)
The V
powered by P12V. P12V is not required during S3/S4/S5
operation. P12V is typically connected to the +12V rail of an
ATX power supply.
VTT REGULATOR
Upper Divider Impedance
Lower Divider Impedance
VREF_OUT Buffer Source Current
Maximum V
LINEAR REGULATORS
DC Gain
Gain Bandwidth Product
Slew Rate
DRIVEn High Output Voltage
DRIVEn Low Output Voltage
DRIVEn High Output Source Current
DRIVEn Low Output Sink Current
VIDPGD
V
V
PROTECTION
OCSET Current Source
V
V
V
V
V
V
V
Thermal Shutdown Limit
TT_GMCH/CPU
TT_GMCH/CPU
TT_DDR
DDQ
DDQ
TT_DDR
TT_DDR
GMCH
TT_GMCH/CPU
TT
OV Level
UV Level
UV Level
regulation circuit and the Linear Drivers are
Current Limit
OV Level
UV Level
TT
Load Current
PARAMETER
Rising Threshold
Falling Threshold
UV Level
5
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics (Continued)
CC_S5
V
V
TT
TT
I
V
V
VREF_OUT
V
V
I
SYMBOL
VTT_MAX
FB4
FB2
I
FB
FB
GBWP
/V
/V
OCSET
T
R
SR
R
) from the
VREF_IN
VREF_IN
/V
/V
SD
/V
/V
U
L
REF
REF
REF
REF
Periodic load applied with 30% duty cycle and
10ms period using ISL6537A_6506EVAL1
evaluation board (see Application Note AN1124)
Guaranteed By Design
DRIVEn Unloaded
V
V
S0
S0
By Design
S0/S3
S0/S3
S0
S0
S0
S0
By Design
FB
FB
ISL6537A
= 770mV, V
= 830mV, V
TEST CONDITIONS
GND (Pins 4, 27, 29)
The GND terminals of the ISL6537A provide the return path
for the V
ground currents are conducted directly through the exposed
paddle of the QFN package which must be electrically
connected to the ground plane through a path as low in
inductance as possible.
UGATE (Pin 26)
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the upper MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
DRIVEn
DRIVEn
= 0V
= 10V
TT
LDO, and switching MOSFET gate drivers. High
9.75
.725
MIN
-3.3
15
18
-3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.700 0.715
TYP
10.0
0.16
1.20
.740
140
115
115
2.5
2.5
1.7
80
20
75
85
75
75
6
-
-
-
-
MAX
0.50
2.00
2.6
3.3
22
2
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UNITS
MHz
V/µs
FN9143.3
mA
mA
mA
kΩ
kΩ
dB
µA
°C
%
%
%
%
%
%
A
V
V
V
V
A