ISL6423B Intersil Corporation, ISL6423B Datasheet - Page 13

• Manufacturer Part Number: ISL6423B
• Description: Single Output LNB Supply and Control Voltage Regulator
• Manufacturer: Intersil Corporation

NOTE: X indicates “Read Only” and is a “Don’t Care” for the Write mode.
Received Data (
The ISL6423B can provide to the master a copy of the
system register information via the I
The read mode is Master activated by sending the chip
address with R/W bit set to 1. At the following Master
generated clock bits, the ISL6423B issues a byte on the
SDA data bus line (MSB transmitted first).
At the ninth clock bit the MCU master can:
• Acknowledge the reception, starting in this way the
• Not acknowledge, stopping the read mode
The read only bits of the register SR1 convey diagnostic
information about the ISL6423B, as indicated in the Table 7.
Power–On I
The I
at power-on. The I
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
interface will not respond to any I
system register SR1 thru SR4 are all initialized to all zero,
thus keeping the power blocks disabled. Once the V
above UVLO, the POWER OK signal to the I
high, and the I
can be configured by the main microprocessor. About 400mV
of hysteresis is provided in the UVLO threshold to avoid false
triggering of the Power-On reset circuit. (I
EN = 0; EN goes HIGH at the same time as (or later than) all
other I
SR4H
transmission of another byte from the ISL6423B.
communication.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
C interface built into the ISL6423B is automatically reset
2
C data for that PWM becomes valid).
SR4M
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
C Interface Reset
C interface becomes operative and the SR’s
2
I
SR4L
C interface block will receive a Power OK
2
C
1
1
1
1
1
1
1
1
1
1
1
1
1
1
bus READ MODE)
EN
13
1
1
1
1
1
1
1
1
1
1
1
1
1
0
2
C commands and the
2
C bus in read mode.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
TABLE 10. CONTROL REGISTER SR4 CONFIGURATION
2
C comes up with
2
C is asserted
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CC
VTOP
rises
X
0
0
0
1
1
0
0
1
1
0
0
1
1
VBOT
X
0
0
1
0
1
0
1
0
1
0
1
0
1
SR4 is selected
VSPEN = SELVTOP = 0, V
VSPEN = SELVTOP = 0, V
VSPEN = SELVTOP = 0, V
VSPEN = SELVTOP = 0, V
VSPEN = 0,SELVTOP = 1, V
VSPEN = 0,SELVTOP = 1, V
VSPEN = 0,SELVTOP = 1, V
VSPEN = 0,SELVTOP = 1, V
VSPEN = 1,SELVTOP = X V
VSPEN = 1,SELVTOP = X V
VSPEN = 1,SELVTOP = X V
VSPEN = 1,SELVTOP = X V
PWM and Linear for channel 1 disabled
ADDR0 and ADDR1 Pins
Connecting these pin to GND the chip I
is 0001000, but, it is possible to choose between four
different addresses by setting these pins to the logic levels
indicated in Table 11.
V
V
V
V
TABLE 11. ADDRESS PIN CHARACTERISTICS
ADDR
ADDR
ADDR
ADDR
V
-1 “0001000”
-2 “0001001”
-3 “0001010”
-4 “0001011”
ADDR
OUT
OUT
OUT
OUT
FUNCTION
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
= 13V, V
= 14V, V
= 13V, V
= 14V, V
= 13V, V
= 14V, V
= 18V, V
= 19V, V
= 18V, V
= 18V, V
= 19V, V
= 19V, V
BOOST
BOOST
BOOST
BOOST
ADDR1
BOOST
BOOST
BOOST
BOOST
BOOST
BOOST
BOOST
BOOST
2
0
0
1
1
C interface address
= 13V + V
= 14V + V
= 13V + V
= 14V + V
= 13V + V
= 14V + V
= 18V + V
= 19V + V
= 18V + V
= 18V + V
= 19V + V
= 19V + V
ADDR0
April 10, 2007
DROP
DROP
DROP
DROP
DROP
DROP
DROP
DROP
0
1
0
1
DROP
DROP
DROP
DROP
FN6412.1