ISL6217 Intersil Corporation, ISL6217 Datasheet
ISL6217
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ISL6217 Summary of contents
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... A precision reference, remote sensing and proprietary architecture, with integrated processor-mode compensated “Droop”, provide excellent static and dynamic CORE voltage regulation. To improve efficiency at light loading, the ISL6217 can be configured to run in single phase PWM in ACTIVE, DEEP or DEEPER SLEEP modes of operation. Another feature of this IC controller is the PGOOD monitor circuit that is held low until CORE voltage increases, during its soft-start sequence, to within 12% of the “ ...
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... Pinout ISL6217 (38 LEAD TSSOP) TOP VIEW VDD 1 DACOUT 2 DSV 3 FSET 4 PWRCH DRSEN 7 DSEN# 8 VID0 9 ISL6217 VID1 10 TSSOP VID2 11 VID3 12 VID4 13 VID5 14 PGOOD 15 EA+ 16 COMP SOFT 19 www.DataSheet4U.com 2 ISL6217 38 VBAT 37 ISEN1 36 PHASE1 35 UG1 34 BOOT1 33 VSSP1 32 LG1 31 VDDP 30 LG2 29 VSSP2 28 BOOT2 27 UG2 ...
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... DACOUT V SOFT SOFT SOFT START EA+ VID0 VID1 VID2 VID VID3 D/A VID4 www.DataSheet4U.com VID5 COMP FB 1.75V OCSET + STV DSV MUX DRSV V CORE REF DSEN# DRSEN 3 ISL6217 PGOOD VDD EN 1.3V POWER- RESET(POR) CONTROL CLOCK AND AND SAWTOOTH FAULT LOGIC GENERATOR + Σ Σ PWM1 PWM2 + ...
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... Intel Pentium“ IV mobile processor using IMVP-IV™ and IMVP-IV+™ voltage positioning. The ISL6217 PWM controller can be configured for two or one channel operation, and the ISL6217 can change the number of power channels in operation, dynamically. The number of channels of operation can be changed through the PWRCH pin ...
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... ISEN Full Scale Input Current Overcurrent Threshold Soft Start Current Droop Current GATE DRIVER 5 ISL6217 Thermal Information Thermal Resistance (Typical, Note 1) TSSOP Package (Note 1) ................................................ 72° Maximum Operating Junction Temperature ..................125 Maximum Storage Temperature Range ..........-65 Maximum Lead Temperature (Soldering 10s) ...............300 + 0 ...
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... Undervoltage Threshold (Vsen/Vref) PGOOD Low Output Voltage LOGIC THRESHOLD EN, DSEN#, DRSEN Low EN, DSEN#, DRSEN High PROTECTION Overvoltage Threshold (Vsen/Vref) www.DataSheet4U.com 6 ISL6217 TEST CONDITIONS 500mA Source Current V UGATE-PHASE = 2.5V 500mA Sink Current V UGATE-PHASE = 2.5V 500mA Source Current V LGATE = 2.5V 500mA Sink Current V LGATE = 2.5V VDDP = 5V, Forward Bias Current = 10mA ...
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... OCSET - A resistor from this pin to ground sets the overcurrent protection threshold. VSEN - This pin is used for remote sensing of the microprocessor CORE voltage. 7 ISL6217 COMP - This pin provides connection to the error amplifier output. 38 VBAT FB - This pin is connected to the inverting input of the error amplifier ...
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... ISL6217. Once the voltage on the EN pin rises above 2.0V, the chip is enabled and soft-start begins. The EN pin of the ISL6217 is also used to reset the ISL6217, for cases when an undervoltage or overcurrent fault condition has latched the IC off. A toggling of the state of this pin to a level below 1 ...
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... PWM drive signals are switched 180° out of phase to reduce ripple current delivered from the DC rail and to the load. The ISL6217 was designed with a 4 amp, low-side gate current sinkability, and a 2 amp low-side gate current source ability, to efficiently drive the latest, high- performance MOSFETs ...
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... Deeper Sleep Modes of Operation 1.292 After initial start-up, a logic high signal on DSEN# and 1.276 logic low signal on DRSEN signals the ISL6217 to operate in Active mode (Refer to Table 2). This mode will recognize 0 0 1.260 VID code changes and regulate the output voltage to these ...
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... FIGURE 7. A logic low signal present on STPCPU# (pin DSEN#), with a logic low signal on DPRSLPVR (pin DRSEN), signals the ISL6217 to reduce the CORE output voltage to the Deep Sleep level, the voltage on the DSV pin. A logic high on DPRSLPVR, (pin DRSEN) with a logic low ...
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... OCSET pin. The voltage on the STV pin will be the voltage the controller will regulate to during the start-up sequence. Once the PGOOD pin of the ISL6217 controller is externally enabled high by the Vccp and Vcc_mch controllers, the ISL6217 will then ramp, after a 10ms delay, to the voltage commanded by the VID setting minus “Droop” ...
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... IMVP-IV+_ SOFT REFERENCE www.DataSheet4U.com ISL6217 FIGURE 9. SIMPLIFIED BLOCK DIAGRAM OF THE ISL6217 VOLTAGE AND CURRENT CONTROL LOOPS FOR A TWO CHANNEL REGULATOR. THE 38 LEAD TSSOP PACKAGE IS SHOWN. 13 ISL6217 Fault Protection The ISL6217 protects the CPU from damaging stress levels. The overcurrent trip point is integral in preventing output shorts of varying degrees from causing current spikes that would damage a CPU ...
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... PGOOD pin for worst case conditions of low supply and largest MOSFET r DSON . Once the proper level of PGOOD current is detected, the ISL6217 then captures the VID and regulates to this value. The PGOOD timer is a function of the internal clock and switching frequency. The internal PGOOD delay can be ...
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... RDROOP and R OCSET . This may happen, as the PTC is not found in every possible resistance value. Selection of R DROOP Figure 11 shows a static “Droop” load line for the 1.484V Active Mode. The ISL6217, as previously mentioned, allows the programming of the load line slope by the selection of the R DROOP resistor. (0A,1.506V) (0A,1 ...
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... As the sense trace for VSEN may be long and routed close to switching nodes, a 1.0mF ceramic decoupling capacitor is located between VSEN and ground at the ISL6217. Output Inductor Selection The output inductor is selected to meet the voltage ripple requirements and minimize the converter response time to a load transient ...
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... MOSFETs body diode. The gate- charge losses are dissipated in the ISL6217 drivers and do not heat the MOSFETs; however, large gate-charge increases the switching time which increases the upper MOSFET switching losses ...
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... Typical Application - 2 Phase Converter Using ISL6217 PWM Controller - 38 Lead TSSOP Figure 14 shows the ISL6217, Synchronous Buck Converter circuit used to provide the CORE voltage regulation for the Intel IMVP-IV™ and IMVP-IV+™ application. The circuit uses 2 channels for delivering up to +5VDC 98.8K_1% 1 µ ...
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... Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19 ISL6217 M38.173 38 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-153-BD-1 ISSUE F) ...