ISL5929 Intersil Corporation, ISL5929 Datasheet
ISL5929
Available stocks
Related parts for ISL5929
ISL5929 Summary of contents
Page 1
... TM Dual 14-Bit, +3.3V, 130/210+MSPS, TM CommLink High Speed D/A Converter The ISL5929 is a dual 14-bit, 130/210+MSPS (Mega Samples Per Second), CMOS, high speed, low power, D/A (digital to analog) converter, designed specifically for use in high performance communication systems such as base transceiver stations utilizing 2. cellular protocols. ...
Page 2
... Typical Applications Circuit ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 (LSB) SLEEP DV PP ICOMP C 1 0.1µ 0.1µF AV +3.3V POWER SOURCE 2 ISL5929 CLK 9 DGND 10 D VDD AGND 11 AGND ...
Page 3
... QD10 QD11 QD12 (MSB) QD13 CLK (LSB) ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 ID10 ID11 ID12 (MSB) ID13 3 ISL5929 INPUT LATCH CASCODE CURRENT SWITCH 40 40 SOURCE MATRIX 31 MSB UPPER SEGMENTS 5-BIT DECODER INT/EXT BIAS VOLTAGE GENERATION REFERENCE ...
Page 4
... IOUTA, QOUTA 16, 21 IOUTB, QOUTB 17 REFIO 18 REFLO 9 SLEEP 4 ISL5929 PIN DESCRIPTION Analog ground. Analog supply (+2.7V to +3.6V). Clock Iinput. Connect to digital ground. Digital supply (+2.7V to +3.6V). Full scale current adjust. Use a resistor to ground to adjust full scale output current. Full scale output current = ...
Page 5
... Output Rise Time Full Scale Step Output Fall Time Full Scale Step Output Capacitance Output Noise IOUTFS = 20mA IOUTFS = 2mA 5 ISL5929 Thermal Information Thermal Resistance (Typical, Note 1) LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C + 0.3V Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150° 0.3V Maximum Lead Temperature (Soldering 10s 300° ...
Page 6
... Reference is not intended to drive an external load Sink/Source Capability Reference Input Impedance Reference Input Multiplying Bandwidth (Note 7) DIGITAL INPUTS D13-D0, CLK Input Logic High Voltage with (Note 3) 3.3V Supply ISL5929 = DV = +3.3V Internal 1.2V, IOUTFS = 20mA REF TEST CONDITIONS = 50 Ω and Ω , Full Scale Output = -2.5dBm ) DIFF ...
Page 7
... Measured with the clock at 200MSPS and the output frequency at 20MHz. 7. See “Definition of Specifications.” 8. Recommended operation is from 3.0V to 3.6V. Operation below 3.0V is possible with some degradation in spectral performance. Reduction in analog output current may be necessary to maintain spectral performance. 9. See Typical Performance Plots. 7 ISL5929 = DV = +3.3V Internal 1.2V, IOUTFS = 20mA REF TEST CONDITIONS = 25° ...
Page 8
... WITH 30kHz RBW FIGURE 3. GSM AT 11MHz, 78MSPS CLOCK (94+dBc @ ∆f = +6MHz, 3dB PAD) FIGURE 5. FOUR EDGE CARRIERS AT 12.4–15.6MHz, 800kHz SPACING, 78MSPS (75+dBc - 20MHz WINDOW) 8 ISL5929 = 100Ω and R = 50Ω) DIFF LOAD FIGURE 2. EDGE AT 11MHz, 78MSPS CLOCK (77dBc -NYQUIST, 6dB PAD) FIGURE 4 ...
Page 9
... FIGURE 9. ONE TONE AT 40.4MHz, 210MSPS CLOCK (61dBc - NYQUIST, 6dB PAD) FIGURE 11. TWO TONES (CF=6) AT 8.5MHz, 50MSPS CLOCK, 500kHz SPACING (83dBc - 10MHz WINDOW, 6dB PAD) 9 ISL5929 = 100Ω and R DIFF SPECTRAL MASK UMTS TDD P>43dBm BTS FIGURE 8. ONE TONE AT 10.1MHz, 80MSPS CLOCK FIGURE 10 ...
Page 10
... W-CDMA standard for cellular applications which uses 3.84MHz modulated carriers. Detailed Description The ISL5929 is a dual 14-bit, current out, CMOS, digital to analog converter. The core of each DAC is based on the ISL5961. The maximum update rate is at least 210+MSPS and can be powered by a single power supply in the recommended range of +3.0V to +3.6V. Operation with clock rates higher than 210MSPS is possible ...
Page 11
... If the internal reference is used, V FSADJ approximately 1.2V external reference is used ISL5929 will equal the external reference. The calculation for I (Full Scale) is: I (Full Scale OUT If the full scale output current is set to 20mA by using the internal voltage reference (1.23V) and a 1.91kΩ ...
Page 12
... I OUT FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM 12 ISL5929 =50Ω. The LOAD R EQ ISL5929 = (2 x OUTA 1:1 Propagation Delay R LOAD The converter requires two clock rising edges for data to be represented at the output. Each rising edge of the clock captures the present data word and outputs the previous data. The propagation delay is therefore 1/CLK, plus < ...
Page 13
... Irvine Center Drive 2401 Palm Bay Rd. Suite 100 Palm Bay, FL 32905 Irvine, CA 92618 TEL: (321) 724-7000 TEL: (949) 341-7000 FAX: (321) 724-7946 FAX: (949) 341-7123 3-13 ISL5929 Q48.7x7A 48 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE SYMBOL -B- e SEATING PLANE A NOTES: 1. Controlling dimension: MILLIMETER. Converted inch ...