ISL1218 Intersil Corporation, ISL1218 Datasheet - Page 4

• Manufacturer Part Number: ISL1218
• Description: I2C Real Time Clock/Calendar
• Manufacturer: Intersil Corporation

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Serial Interface Specifications
NOTES:
Hysteresis
V
Cpin
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cb
Rpu
2. IRQ and F
3. LPMODE = 0 (default).
4. In order to ensure proper timekeeping, the V
5. Typical values are for T = 25°C and 3.3V supply voltage.
6. These are I
7. A write to register 08h should only be done if V
SCL
IN
AA
BUF
LOW
HIGH
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
HD:STO
DH
R
F
OL
SYMBOL
OUT
SDA and SCL Input Buffer Hysteresis
SDA Output Buffer LOW Voltage,
Sinking 3mA
SDA and SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at SDA
and SCL Inputs
SCL Falling Edge to SDA Output Data
Valid
Time the Bus Must be Free before the
Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input daTa Setup Time
Input Data Hold Time
STOP Condition Setup Time
STOP Condition Hold Time
Output Data Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
SDA and SCL Bus Pull-up Resistor
Off-chip
2
C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
Inactive.
PARAMETER
4
Over the recommended operating conditions unless otherwise specified. (Continued)
DD SR-
DD
> V
T
V
Any pulse narrower than the max spec
is suppressed.
SCL falling edge crossing 30% of V
until SDA exits the 30% to 70% of V
window.
SDA crossing 70% of V
STOP condition, to SDA crossing 70%
of V
condition.
Measured at the 30% of V
Measured at the 70% of V
SCL rising edge to SDA falling edge.
Both crossing 70% of V
From SDA falling edge crossing 30% of
V
of V
From SDA exiting the 30% to 70% of
V
crossing 30% of V
From SCL falling edge crossing 30% of
V
of V
From SCL rising edge crossing 70% of
V
of V
From SDA rising edge to SCL falling
edge. Both crossing 70% of V
From SCL falling edge crossing 30% of
V
of V
From 30% to 70% of V
From 70% to 30% of V
Total on-chip and off-chip
Maximum is determined by t
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
specification must be followed.
A
IN
DD
DD
DD
DD
DD
BAT
= 25°C, f = 1MHz, V
DD
DD
DD
DD
DD
= 0V, V
, to SDA rising edge crossing 30%
, until SDA enters the 30% to 70%
to SCL falling edge crossing 70%
window, to SCL rising edge
to SDA entering the 30% to 70%
, otherwise the device will be unable to communicate using I
.
.
during the following START
window.
window.
TEST CONDITIONS
ISL1218
OUT
= 0V
DD
DD
DD
DD
DD
DD
DD
DD
.
= 5V,
during a
R
crossing.
crossing.
DD
and t
.
DD
DD
F
.
,
0.1 x Cb
0.1 x Cb
0.05 x
1300
1300
MIN
V
20 +
20 +
600
600
600
100
600
600
10
DD
0
0
0
1
(Note 5)
TYP
MAX
400
900
900
300
300
400
0.4
10
50
2
C.
UNITS
kHz
pF
pF
kΩ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
June 22, 2006
NOTES
FN6313.0
6
6
6
6