EMC1424 SMSC Corporation, EMC1424 Datasheet - Page 31

• Manufacturer Part Number: EMC1424
• Description: (EMC1423 / EMC1424) Temperature Sensor
• Manufacturer: SMSC Corporation

ADDR
ADDR
03h
09h
02h
1°C Temperature Sensor with Hardware Thermal Shutdown
Datasheet
SMSC EMC1423/EMC1424
6.3
6.4
R/W
R/W
R/W
R
Status Register
Configuration Register
The Status Register reports general error conditions. To identify specific channels, refer to
Section
appropriate High Limit, Low Limit, or THERM Limit register has been read or cleared.
Bit 7 - BUSY - This bit indicates that the ADC is currently converting. This bit does not cause either
the ALERT or THERM pin to be asserted.
Bit 4 - HIGH - This bit is set when any of the temperature channels exceeds its programmed high limit.
See the High Limit Status Register for specific channel information
will assert the ALERT pin.
Bit 3 - LOW - This bit is set when any of the temperature channels drops below its programmed low
limit. See the Low Limit Status Register for specific channel information
bit will assert the ALERT pin.
Bit 2 - FAULT - This bit is asserted when a diode fault is detected on any of the external diode
channels. See the External Diode Fault Register for specific channel information
set, this bit will assert the ALERT pin.
Bit 1 - THERM - This bit is set when the any of the temperature channels exceeds its programmed
THERM limit. See the THERM Limit Status Register for specific channel information
Bit 0 - HWSD - This bit is set when the External Diode 1 Temperature exceeds the Hardware Thermal
Shutdown Limit set by the pull-up resistors on the ALERT and SYS_SHDN pins. When set, this bit will
assert the SYS_SHDN pin.
The Configuration Register controls the basic operation of the device. This register is fully accessible
at either address.
Bit 7 - MASK_ALL - Masks the ALERT pin from asserting.
Bit 5 - ALERT/COMP - Controls the operation of the ALERT pin.
Configuration
REGISTER
‘0’ (default) - The ALERT pin is not masked. If any of the appropriate status bits are set the ALERT
pin will be asserted.
‘1’ - The ALERT pin is masked. It will not be asserted for any interrupt condition unless it is
configured as a THERM pin. The Status Registers will be updated normally.
‘0’ (default) - The ALERT pin acts as described in
‘1’ - The ALERT pin acts in comparator mode as described in
MASK_ALL bit is ignored.
REGISTER
Status
6.16,
Section
MASK
_ALL
B7
BUSY
B7
6.17, and
Table 6.4 Configuration Register
B6
-
B6
-
Table 6.3 Status Register
Section
ALERT/
DATASHEET
COMP
B5
B5
-
6.18. The individual Status Register bits are cleared when the
31
HIGH
B4
-
B4
Section
RECD
LOW
B3
B3
2
5.3.
FAULT
RANGE
B2
B2
Section
(Section
(Section
THERM
DAVG_
5.3.2. In this mode the
B1
DIS
B1
6.16). When set, this bit
Revision 1.16 (03-15-07)
6.17). When set, this
(Section
HWSD
APDD
B0
(Section
B0
-
Section
6.9). When
DEFAULT
6.18).
DEFAULT
00h
00h
6.9,