MC1455B ON Semiconductor, MC1455B Datasheet - Page 5

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MC1455B

Manufacturer Part Number
MC1455B
Description
Timers
Manufacturer
ON Semiconductor
Datasheet

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external resistor − capacitor network as its timing element. It
can be used in both the monostable (one−shot) and astable
modes with frequency and duty cycle controlled by the
capacitor and resistor values. While the timing is dependent
upon the external passive components, the monolithic circuit
provides the starting circuit, voltage comparison and other
functions needed for a complete timing circuit. Internal to the
integrated circuit are two comparators, one for the input
signal and the other for capacitor voltage; also a flip−flop and
digital output are included. The comparator reference
voltages are always a fixed ratio of the supply voltage thus
providing output timing independent of supply voltage.
Monostable Mode
are used for the timing network. Both the threshold terminal
and the discharge transistor terminal are connected together
in this mode (refer to circuit in Figure 14). When the input
voltage to the trigger comparator falls below 1/3 V
comparator output triggers the flip−flop so that its output
sets low. This turns the capacitor discharge transistor “off”
and drives the digital output to the high state. This condition
allows the capacitor to charge at an exponential rate which
is set by the RC time constant. When the capacitor voltage
reaches 2/3 V
flip−flop. This action discharges the timing capacitor and
returns the digital output to the low state. Once the flip−flop
The MC1455 is a monolithic timing circuit which uses an
In the monostable mode, a capacitor and a single resistor
Threshold
Discharge
Trigger
Reset
CC
V
Gnd
CC
, the threshold comparator resets the
Reset
4.7 k
Discharge
10 k
Comparator
Threshold
Figure 13. Representative Circuit Schematic
830
MC1455, MC1455B, NCV1455B
100
100 k
4.7 k
GENERAL OPERATION
CC
http://onsemi.com
, the
Comparator
1.0 k
Trigger
5
5.0 k
5.0 k
5.0 k
has been triggered by an input signal, it cannot be retriggered
until the present timing period has been completed. The time
that the output is high is given by the equation t = 1.1 R
Various combinations of R and C and their associated times
are shown in Figure 16. The trigger pulse width must be less
than the timing period.
interrupting the timing cycle. As long as the reset pin is low,
the capacitor discharge transistor is turned “on” and
prevents the capacitor from charging. While the reset
voltage is applied the digital output will remain the same.
The reset pin should be tied to the supply voltage when not
in use.
A reset pin is provided to discharge the capacitor, thus
Control Voltage
R
R
L
L
c b
Trigger
Output
e
3
2
Figure 14. Monostable Circuit
Flip−Flop
7.0 k
4.7 k
+V
Reset
CC
(5.0 V to 15 V)
4
6.8 k
MC1455
1
c
4.7 k
V
8
220
Output
CC
3.9 k
Threshold
Control
Voltage
b
Discharge
7
6
5
Output
0.01 mF
R
C
A
A
C.

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