MC12429FN Motorola, MC12429FN Datasheet

MC12429FN

Manufacturer Part Number

MC12429FN

Description

HIGH FREQUENCY PLL CLOCK GENERATOR

Manufacturer

Motorola

Datasheet

1.MC12429FN.pdf (10 pages)

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

High Frequency Clock Generator

applications that require both serial and parallel interfaces. Its internal

VCO will operate over a range of frequencies from 400 to 800MHz. The

differential PECL output can be configured to be the VCO frequency

divided by 2, 4, 8 or 16. With the output configured to divide the VCO

frequency by 2, and with a 16.000MHz external quartz crystal used to

provide the reference frequency, the output frequency can be specified in

1MHz steps. The PLL loop filter is fully integrated so that no external

components are required.

Functional Description

its frequency reference. The output of the reference oscillator is divided

by 8 before being sent to the phase detector. With a 16MHz crystal, this

provides a reference frequency of 2MHz. Although this data sheet

illustrates functionality only for a 16MHz crystal, any crystal in the

10–25MHz range can be used.

the serial or parallel interfaces. The output of this loop divider is also applied to the phase detector.

adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock.

(N divider) is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (2, 4, 8, or

16). This divider extends performance of the part while providing a 50% duty cycle.

in 50 to V CC – 2.0. The positive reference for the output driver and the internal logic is separated from the power supply for the

phase–locked loop to minimize noise induced jitter.

inputs to configure the internal counters. Normally, on system reset, the P_LOAD input is held LOW until sometime after power

becomes valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority

over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs to reduce component count in the

application of the chip.

The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The

configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input. See the

programming section for more information.

1/97

Motorola, Inc. 1997

25 to 400MHz Differential PECL Outputs

Fully Integrated Phase–Locked Loop

Minimal Frequency Over–Shoot

Synthesized Architecture

Serial 3–Wire Interface

Parallel Interface for Power–Up

Quartz Crystal Interface

28–Lead PLCC Package

Operates from 3.3V or 5.0V Power Supply

The MC12429 is a general purpose synthesized clock source targeting

The internal oscillator uses the external quartz crystal as the basis of

The VCO within the PLL operates over a range of 400 to 800MHz. Its output is scaled by a divider that is configured by either

The phase detector and loop filter attempt to force the VCO output frequency to be M times the reference frequency by

The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider

The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated

The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]

The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.

The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the

25ps Peak–to–Peak Output Jitter

REV 5

HIGH FREQUENCY PLL

CLOCK GENERATOR

28–LEAD PLCC PACKAGE

MC12429

CASE 776–02

FN SUFFIX

Related parts for MC12429FN

MC12429FN Summary of contents

Page 1

... HIGH–to–LOW edge of the S_LOAD input. See the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the programming section for more information. 1/97 Motorola, Inc. 1997 1 REV 5 MC12429 HIGH FREQUENCY PLL ...

Page 2

... This is the positive supply for the PLL, and should be as noise–free as possible for low–jitter operation. This supply is connected to +3. PLL_V CC ). Current drain through PLL_V CC GND These pins are the negative supply for the chip and are normally all connected to ground. MOTOROLA V CC TEST GND 22 ...

Page 3

... For computer applications another useful frequency base would be 16.666MHz. From this reference one can generate 8 a family of output frequencies at multiples of the 33.333MHz PCI clock example to generate a 133.333MHz clock 3 MC12429 +3.3 or 5.0V V CC0 25 24 FOUT 23 FOUT 20 TEST LATCH 3–BIT SR 22 and FOUT. N. MOTOROLA ...

Page 4

... S_DATA S_LOAD M[8: N[1:0] P_LOAD MOTOROLA The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream not configurable through the N parallel interface. Although it is possible to select the node that represents FOUT, the CMOS output may not be able to toggle fast enough for some of the higher output frequencies. The T2, T1 and T0 control bits are preset to ‘ ...

Page 5

... FOUT FOUT 1.41 FOUT PLL_V MC12429 FOUT N DIVIDE ( 16) (VIA ENABLE GATE) 7 TEST TEST MUX 0 Max Unit Condition 3.3 to 5.0V 0 3.3 to 5.0V 1 –0.8mA 0 0.8mA 2. CC0 = 3.3V (Notes 1., 2.) 1. CC0 = 3.3V (Notes 1., 2.) 100 mA 20 MOTOROLA ...

Page 6

... Unfortunately most crystals are characterized in a parallel resonant mode. Fortunately there is no physical difference between a series resonant and a parallel resonant crystal. The difference is purely in the way the devices are MOTOROLA Min Max S_CLOCK 10 ...

Page 7

... 10– 0. 0.1 F É É É É = GND = Via MOTOROLA ...

Page 8

... Unfortunately with today’s high performance measurement equipment there is no way to measure this parameter for jitter performance in the class MOTOROLA demonstrated by the MC12429 result different methods are used which approximate cycle–to–cycle jitter. The typical ...

Page 9

... T L– 0.010 (0.250 L– 0.007 (0.180 L– 0.007 (0.180) T L– MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0. 10.42 10.92 1.02 ––– MOTOROLA ...

Page 10

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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