MC10131 ON Semiconductor, MC10131 Datasheet

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MC10131

Manufacturer Part Number
MC10131
Description
Dual TYPE D Master-Slave Flip-Flop
Manufacturer
ON Semiconductor
Datasheet

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Asynchronous Set (S) and Reset (R) override Clock (C
Enable (C
holding the common clock in the low state and using the enable inputs
for the clocking function. If the common clock is to be used to clock
the flip–flop, the Clock Enable inputs must be in the low state. In this
case, the enable inputs perform the function of controlling the
common clock.
the clock. A change in the information present at the data (D) input
will not affect the output information at any other time due to master
slave construction.
January, 2002 – Rev. 7
The MC10131 is a dual master–slave type D flip–flop.
The output states of the flip–flop change on the positive transition of
P
F
t
t
Semiconductor Components Industries, LLC, 2002
pd
r
, t
D
Tog
= 3.0 ns typ
f
= 235 mW typ/pkg (No Load)
= 2.5 ns typ (20%–80%)
= 160 MHz typ
For PLCC pin assignment, see the Pin Conversion Tables on page 18
E
) inputs. Each flip–flop may be clocked separately by
of the ON Semiconductor MECL Data Book (DL122/D).
Pin assignment is for Dual–in–Line Package.
DIP PIN ASSIGNMENT
LOGIC DIAGRAM
www.DataSheet4U.com
C
) and Clock
1
C = C
high state.
N.D. = Not Defined
MC10131L
MC10131P
MC10131FN
Device
E
+ C
H
H
H
H
C
L
R
L
L
C.
ORDERING INFORMATION
CLOCKED TRUTH TABLE
A
WL = Wafer Lot
YY = Year
WW = Work Week
A clock H is a clock transition from a low to a
R–S TRUTH TABLE
http://onsemi.com
= Assembly Location
FN SUFFIX
CASE 620
CASE 648
CASE 775
P SUFFIX
L SUFFIX
PLCC–20
CDIP–16
PDIP–16
PLCC–20
CDIP–16
PDIP–16
Package
H
H
H
X
L
L
L
D
S
Publication Order Number:
16
16
1
1
25 Units / Rail
25 Units / Rail
46 Units / Rail
DIAGRAMS
MARKING
AWLYYWW
AWLYYWW
AWLYYWW
MC10131L
MC10131P
Shipping
10131
Q
Q
MC10131/D
N.D.
Q
Q
H
H
n+1
L
n+1
L
1
n
n

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MC10131 Summary of contents

Page 1

... The MC10131 is a dual master–slave type D flip–flop. Asynchronous Set (S) and Reset (R) override Clock (C Enable (C ) inputs. Each flip–flop may be clocked separately by E holding the common clock in the low state and using the enable inputs for the clocking function. If the common clock used to clock the flip– ...

Page 2

... Setup Time t setup Hold Time t hold Toggle Frequency (Max) f tog * Individually test each input applying Output level to be measured after a clock pulse has been applied to the C MC10131 Test Limits Pin –30 C Under Under Test Min Max Min 525 ...

Page 3

... The circuit test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. MC10131 TEST VOLTAGE VALUES (Volts) V ...

Page 4

... Y BRK –L– –M– –T– J VIEW S G1 MC10131 PACKAGE DIMENSIONS PLCC–20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE VIEW D– VIEW S http://onsemi.com ...

Page 5

... –A– –T– MC10131 PACKAGE DIMENSIONS CDIP–16 L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE PDIP–16 P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R ...

Page 6

... Notes MC10131 http://onsemi.com 6 ...

Page 7

... Notes MC10131 http://onsemi.com 7 ...

Page 8

... N. American Technical Support: 800–282–9855 Toll Free USA/Canada MC10131 JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 MC10131/D ...

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