MC100LVEL92DW Motorola, MC100LVEL92DW Datasheet

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MC100LVEL92DW

Manufacturer Part Number
MC100LVEL92DW
Description
Triple PECL to LVPECL Translator
Manufacturer
Motorola
Datasheet
1.MC100LVEL92DW.pdf (3 pages)

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Triple PECL to LVPECL
Translator
receives standard PECL signals and translates them to differential
LVPECL output signals.
signals at the inputs. If a single ended PECL input is to be used the PECL
V BB output should be connected to the D input and the active signal will
drive the D input. When used the PECL V BB should be bypassed to
ground via a 0.01 f capacitor. The PECL V BB is designed to act as a
switching reference for the MC100LVEL92 under single ended input
conditions, as a result the pin can only source/sink 0.5mA of current.
MC100LVEL92 requires three power rails. The V CC supply is to be
connected to the standard PECL supply, the LVCC supply is to be
connected to the LVPECL supply, and Ground is connected to the system
ground plane. Both the V CC and LVCC should be bypassed to ground
with a 0.01 f capacitor.
voltage level and the D input will be pulled to ground. This condition will
force the “Q” output low, ensuring stability.
7/97
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1997
500ps Propagation Delays
Fully Differential Design
20–Lead SOIC Package
5V and 3.3V Supplies Required
>1500V ESD
A PECL V BB output is provided for interfacing single ended PECL
To accomplish the PECL to LVPECL level translation, the
Under open input conditions, the D input will be biased at a V CC /2
The MC100LVEL92 is a triple PECL to LVPECL translator. The device
Logic Diagram and Pinout: 20-Lead SOIC (Top View)
LVPECL
V CC
V CC
20
1
PECL
Q0
19
D0
2
Q0
18
D0
3
LVCC
LVPECL
PECL
V BB
17
4
PECL
Q1
16
D1
5
Q1
D1
15
6
4–1
LVPECL
PECL
LVCC
V BB
14
7
PECL
Q2
D2
13
8
Q2
D2
12
9
GND
V CC
11
10
PIN NAMES
Pins
Dn
Qn
V BB
LVCC
V CC
GND
REV 2
MC100LVEL92
PLASTIC SOIC PACKAGE
Function
PECL Inputs
LVPECL Outputs
PECL Reference Voltage Output
V CC for LVPECL Output
V CC for PECL Inputs
Common Ground Rail
CASE 751D-04
20
DW SUFFIX
1

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MC100LVEL92DW Summary of contents

Page 1

... Logic Diagram and Pinout: 20-Lead SOIC (Top View LVCC LVPECL LVPECL PECL PECL PECL 7/97 Motorola, Inc. 1997 PIN NAMES Pins LVCC V CC GND Q1 LVCC LVPECL PECL ...

Page 2

... Minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40. 7. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V PP min and 1V. MOTOROLA ...

Page 3

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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