SST39VF160 Silicon Storage Technology, SST39VF160 Datasheet - Page 3

• Manufacturer Part Number: SST39VF160
• Description: 16 Megabit (1M x 16-Bit) Multi-Purpose Flash
• Manufacturer: Silicon Storage Technology

16 Megabit Multi-Purpose Flash
SST39VF160Q / SST39VF160
Advance Information
then ready for the next operation. During internal Erase
operation, any attempt to read DQ7 will produce a ‘0’. Once
the internal Erase operation is completed, DQ7 will pro-
duce a ‘1’. The Data# Polling is valid after the rising edge
of fourth WE# (or CE#) pulse for Program operation. For
Sector or Chip Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 6 for
Data# Polling timing diagram and Figure 17 for a flowchart.
Toggle Bit (DQ
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
and 0’s, i.e., toggling between 1 and 0. The toggle bit will
begin with ‘1’. When the internal Program or Erase opera-
tion is completed, the DQ6 bit will stop toggling. The device
is then ready for the next operation. The Toggle Bit is valid
after the rising edge of fourth WE# (or CE#) pulse for
Program operation. For Sector or Chip Erase, the Toggle
Bit is valid after the rising edge of sixth WE# (or CE#) pulse.
See Figure 7 for Toggle Bit timing diagram and Figure 18
for a flowchart.
Data Protection
The SST39VF160Q/VF160 provide both hardware and
software features to protect nonvolatile data from inadvert-
ent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than
5 ns will not initiate a write cycle.
V
inhibited when V
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39VF160Q/VF160 provide the JEDEC approved
Software Data Protection scheme for all data alteration
operations, i.e., Program and Erase. Any Program opera-
tion requires the inclusion of the three byte sequence. The
three byte-load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six byte sequence. The SST39VF160Q/VF160 device is
shipped with the software data protection permanently
enabled. See Table 4 for the specific software command
codes. During SDP command sequence, invalid com-
mands will abort the device to read mode within T
contents of DQ
command sequence.
© 1998 Silicon Storage Technology, Inc.
DD
Power Up/Down Detection: The Write operation is
15
6
DD
)
-DQ
is less than 1.5V.
8
are “Don’t Care” during any SDP
6
will produce alternating 1’s
RC
. The
3
Common Flash Memory Interface (CFI)
The SST39VF160Q/VF160 also contain the CFI informa-
tion to describe the characteristics of the device. In order
to enter the CFI query mode, the system must write 3 byte
sequence, same as product ID entry command with 98H
(CFI query command) to address 5555H in the last byte
sequence. Once the device enters the CFI query mode, the
system can read CFI data at the addresses given in tables
5 through 8. The system must write the reset command to
return to read mode from the CFI query mode.
Product Identification
The Product Identification mode identifies the devices as
the SST39VF160Q, SST39VF160 and manufacturer as
SST. This mode may be accessed by hardware or soft-
ware operations. The hardware operation is typically used
by a programmer to identify the correct algorithm for the
SST39VF160Q/VF160. Users may wish to use the soft-
ware product identification operation to identify the part
(i.e., using the device code) when using multiple manufac-
turers in the same socket. For details, see Table 3 for
hardware operation or Table 4 for software operation,
Figure 9 for the software ID entry and read timing diagram
and Figure 18 for the ID entry command sequence flow-
chart.
T
This command may also be used to reset the device to the
read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly.
V
This feature is available only on the SST39VF160Q. This
pin functions as power supply pin for input/output buffers.
It should be tied to V
It should be tied to a 5.0V±10% (4.5V - 5.5V) power supply
in a mixed voltage system environment where flash
memory has to be interfaced with 5V system chips. The
V
No Connect pin.
DDQ
DDQ
ABLE
Manufacturer’s Code
Device Code
pin is not offered on the SST39VF160, instead it is a
- I/O Power Supply
1: P
RODUCT
I
DENTIFICATION
DD
(2.7V - 3.6V) in a 3.0V-only system.
Address
0000H
0001H
T
ABLE
00BFH
2782H
Data
329 PGM T1.1
329-09 11/98
5
6
7
8
13
14
15
16
1
2
3
4
9
10
11
12