SST36VF1602C SST, SST36VF1602C Datasheet - Page 4

• Manufacturer Part Number: SST36VF1602C
• Description: (SST36VF1601C / SST36VF1602C) 16 Mbit (x8/x16) Dual-Bank Flash Memory
• Manufacturer: SST

Data Sheet
Toggle Bits (DQ
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
stop toggling. The device is then ready for the next opera-
tion. The toggle bit is valid after the rising edge of the fourth
WE# (or CE#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ
rising edge of sixth WE# (or CE#) pulse. DQ
“1” if a Read operation is attempted on an Erase-sus-
pended Sector/Block. If Program operation is initiated in a
sector/block not selected in Erase-Suspend mode, DQ
toggle.
An additional Toggle Bit is available on DQ
used in conjunction with DQ
sector is being actively erased or erase-suspended. Table 1
shows detailed status bit information. The Toggle Bit (DQ
is valid after the rising edge of the last WE# (or CE#) pulse
of a Write operation. See Figure 11 for Toggle Bit timing
diagram and Figure 24 for a flowchart.
TABLE 1: W
Note: DQ
Data Protection
The devices provide both hardware and software features
to protect nonvolatile data from inadvertent writes.
©2006 Silicon Storage Technology, Inc.
Status
Normal
Operation
Erase-
Suspend
Mode
status information.
7,
DQ
Standard
Program
Standard
Erase
Read From
Erase
Suspended
Sector/Block
Read From
Non-Erase
Suspended
Sector/Block
Program
6,
and DQ
RITE
O
2
6
PERATION
require a valid address when reading
and DQ
DQ7#
DQ7#
Data
DQ
0
1
7
6
6
to check whether a particular
will produce alternating “1”s
Toggle
Toggle
Toggle
Data
DQ
1
S
2
6
TATUS
)
No Toggle
No Toggle
6
Toggle
Toggle
) is valid after the
Data
DQ
2
, which can be
6
2
will be set to
RY/BY#
6
T1.2 1249
bit will
0
0
1
1
0
6
will
2
)
4
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
V
inhibited when V
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The devices provide hardware block protection which pro-
tects the outermost 8 KWord in the larger bank. The block
is protected when WP# is held low. See Figures 1, 2, 3,
and 4 for Block-Protection location.
A user can disable block protection by driving WP# high.
This allows data to be erased or programmed into the pro-
tected sectors. WP# must be held high prior to issuing the
Write command and remain stable until after the entire
Write operation has completed.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
devices to read array data. When the RST# pin is held low
for at least T
return to Read mode (see Figure 20). When no internal
Program/Erase operation is in progress, a minimum period
of T
Read can take place (see Figure 19).
The Erase operation that has been interrupted needs to be
re-initiated after the device resumes normal operation
mode to ensure data integrity.
Software Data Protection (SDP)
These devices provide the JEDEC standard Software Data
Protection scheme for all data alteration operations, i.e.,
Program and Erase. Any Program operation requires the
inclusion of the three-byte sequence. The three-byte load
sequence is used to initiate the Program operation, provid-
ing optimal protection from inadvertent Write operations,
e.g., during the system power-up or power-down. Any
Erase operation requires the inclusion of the six-byte
sequence. The devices are shipped with the Software Data
Protection permanently enabled. See Table 5 for the spe-
cific software command codes. During SDP command
sequence, invalid commands will abort the device to Read
mode within T
V
sequence.
DD
IH,
RHR
Power Up/Down Detection: The Write operation is
but no other value during any SDP command
is required after RST# is driven high before a valid
16 Mbit Dual-Bank Flash Memory
SST36VF1601C / SST36VF1602C
RP ,
RC.
any in-progress operation will terminate and
DD
The contents of DQ
is less than 1.5V.
15
-DQ
S71249-06-000
8
can be V
IL
1/06
or