P123-08H PhaseLink Corp., P123-08H Datasheet - Page 4

• Manufacturer Part Number: P123-08H
• Description: 3.3v Zero Delay Buffer
• Manufacturer: PhaseLink Corp.

LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
- Keep traces short
- Trace = Inductor. With a capacitive load, equals
- Long trace = Transmission Line. Without proper
- Design long traces as “striplines” or “microstrips”
- Terminate traces with characteristic impedance of
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ringing
termination this will cause reflections (causing
ringing).
with defined impedance.
the trace to avoid reflections (see figure below).
( Typical buffer impedance 20Ω)
CMOS Output Buffer
Place Series Resistor as close as possible to CMOS output
Adjust value to match output buffer
impedance to 50 Ω trace. Typical
Series Resistor
value 30 Ω.
Typical CMOS termination
Decoupling and Power Supply Considerations
- Place decoupling capacitors as close as possible to
- Multiple VDD pins should be decoupled separately
- Value of decoupling capacitor is frequency de-
the VDD pin(s) to bypass noise from the power
supply
for best performance.
pendant. Typical values to use are 0.1μF for de-
signs supporting frequencies below 50MHz
(0.01μF for designs supporting frequencies above
50MHz).
50 Ω line
(Preliminary)
3.3V Zero Delay Buffer
To CMOS Input
PL123-08