P123-042 PhaseLink Corp., P123-042 Datasheet - Page 2

• Manufacturer Part Number: P123-042
• Description: 3.3v Zero Delay Buffer
• Manufacturer: PhaseLink Corp.

The PLL’s feedback path must be closed by connecting
FBK to one of the available four outputs. The output
driving the FBK pin will drive an (internal) pin load of
7pF plus any additional loading placed on this output
pin.
For zero-delay applications, all outputs, including the
FBK pin connected to an output pin, must be loaded
equally. Varying the loading between the FBK pin and
output pins can adjust the input-to-output delay.
PIN DESCRIPTION
Notes: 1: Weak pull-down.
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 7/19/07 Page 2
Pin
1
2
3
4
5
6
7
8
2: Weak pull-down on all outputs.
CLKA1
CLKA2
CLKB1
CLKB2
Name
REF
GND
VDD
FBK
[1]
[2]
[2]
[2]
[2]
Type
O
O
O
O
P
P
I
I
Input reference frequency
Clock output, Bank A
Clock output, Bank A
Ground
Clock output, Bank B
Clock output, Bank B
3.3V Supply
PLL feedback input
MAXIMUM RATINGS
Supply Voltage to Ground Potential……………-0.5V to 4.6V
DC Input Voltage (Except REF)…..…..…-0.5V to VDD+0.5V
DC Input Voltage REF…………………………….-0.5V to 4.6V
Storage Temperature………………………...…..-65 to 150 °C
Junction Temperature…………………………………….150 °C
Static Discharge Voltage
Description
3.3V Zero Delay Buffer
(Preliminary)
(MIL-STD-883, Method 3015).
PL123-04
.> 2KV