TS8388B ATMEL Corporation, TS8388B Datasheet
TS8388B
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TS8388B Summary of contents
Page 1
... Electronic Countermeasures/Electronic Warfare • Direct RF Down-conversion Description The TS8388B is a monolithic 8-bit analog-to-digital converter, designed for digitizing wide bandwidth analog signals at very high sampling rates GSPS. The TS8388B uses an innovative architecture, including an on-chip Sample and Hold (S/H), and is fabricated with an advanced high speed bipolar process ...
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... CLK, CLKB CLOCK BUFFER DRRB DR, DRB Functional The TS8388B is an 8-bit 1 GSPS ADC based on an advanced high-speed bipolar technology featuring a cutoff frequency of 25 GHz. Description The TS8388B includes a front-end master/slave Track and Hold stage (S/H), followed by an analog encoding stage and interpolation circuitry. ...
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... Absolute maximum ratings are limiting values (referenced to GND = 0V applied individually, while other parameters are within specified operating conditions. Long exposure to maximum rating may affect device reliability. The use of a thermal heat sink is mandatory. See “The board set comes fully assembled and tested, with the TS8388B installed.” on page 42. Recommended ...
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... Positive supply voltage Digital (LVDS) Positive supply current Negative supply voltage Negative supply current Nominal power dissipation Power supply rejection ratio Power Requirements Power Requirements (CQFP68 packaged device) Positive supply voltage Digital (LVDS) TS8388B 4 Comments V 50 differential or single-ended IN, INB - V IN INB P ...
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... SSBW 4 – – ): – 4 CLKB V – – – – IH – – – CLK TS8388B Value Min Typ Max Unit – 385 445 mA – 395 445 mA – 115 145 mA – 120 145 mA -5.3 -5 -4.7 V – 165 200 mA – ...
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... Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format Tj (typical Differential non linearity Differential non linearity Integral non linearity Integral non linearity No missing codes Gain Input offset voltage TS8388B 6 Value Test Symbol Level Min Typ – ...
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... BER 4 – – TOR 4 – – – SINAD TS8388B Typ Max Unit Note 125 150 ppm ppm/ C -0.25 – lsb (2)(3) -0.35 – lsb 0.3 0.6 lsb 0.4 0.7 lsb 0.7 – lsb (2)(3) 0.9 – lsb ...
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... Minimum clock frequency Minimum Clock pulse width (high) Minimum Clock pulse width (low) Aperture delay Aperture uncertainty Data output delay Output rise/fall time for DATA (20% – 80%) Output rise/fall time for DATA READY (20% – 80%) TS8388B 8 Value Test Symbol Level Min Typ – ...
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... Histogram testing based on sampling MHz sinewave at 50 MSPS. 4. Output error amplitude < ± 4 lsb around correct code (including gain and offset error). 5. Maximum jitter value obtained for single-ended clock input on the JTS8388B die (chip on board): 200 fs. (500 fs expected on TS8388BG) 6. Digital output back termination options depicted in Application Notes. ...
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... Timing Diagrams Figure 2. TS8388B Timing Diagram (1 GSPS Clock Rate), Data Ready Reset, Clock Held at LOW Level (VIN, VINB) X N-1 (CLK, CLKB) 1360 ps DIGITAL 1000 ps OUTPUTS TDR = 1320 ps Data Ready (DR, DRB) DRRB Figure 3. TS8388B Timing Diagram (1 GSPS Clock Rate), Data Ready Reset, Clock Held at HIGH Level ...
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... Only MIN and MAX values are guaranteed (typical values are issuing from characterization results). (1) (2) (for “C” Temperature range ). (1) , and sample tested at specified temperatures (2) ). (2) ). VPLUSD = +0V (ECL) VCC = +5V VPLUSD = +2.4V (LVDS) VIN VINB CLK TS8388B CLKB 16 GAIN GORG DIOD/ DRRB DVEE = -5V VEE = -5V GND TS8388B OR ORB D0 D7 D0B D7B DR DRB 11 ...
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... Negative 1/2 scale - 1/2 lsb -249 mV Negative full scale + 1/2 lsb -251 mV Negative full scale - 1/2 lsb < -251 mV < Negative full scale - 1/2 lsb TS8388B 12 Digital Output Binary GORB = VCC or Floating ...
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... Package Description Pin Description Table 7. TS8388BGL Pin Description (CBGA68 package) Symbol Pin number GND A2, A5, B1, B5, B10, C2, D2, E1, E2, E11, F1, F2, G11, K2, K3, K4, K5, K10, L2 A4, A6, B2, B4, B6, H1, H2, L6 A3, B3, G1, G2, J1 F10, F11 ...
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... TS8388BGL Pinout Figure 4. TS8388BGL Pinout of CBGA 68 Package Gorb 6 VCC 5 GND 4 VCC 3 VEE 2 GND 1 NC Ball A1 Index A other side TS8388B 14 VPLUSD B3b DRb GND DVEE GND GND VPLUSD B3 DR DVEE B4b B2b B1b B0b VCC GND VCC VEE ...
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... Table 8. TS8388BF/TS8388BFS Pin Description (CQFP68 package) Symbol Pin number GND 5, 13, 27, 28, 34, 35, 36, 41, 42, 43, 50, 51, 52, 53, 58 16, 17, 18, 68 PLUSD V 26, 29, 32, 33, 46, 47 30, 31, 44 (1) V 56, 57 INB (1) CLK (1) CLKB ...
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... TS8388BF/ TS8388BFS Pinout Figure 5. TS8388BF/TS8388BFS Pinout of CQFP68 package VPLUSD D2B D1B D0B 25 GORB VCC 26 27 GND 28 GND 29 VCC 30 VEE 31 VEE VCC 32 33 VCC 34 GND TS8388B 16 TOP VIEW ...
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... MSPS/F S Figure 6. Integral Non Linearity Note: Figure 7. Differential Non Linearity Note: 2144C–BDC–04/ MHz IN Clock Frequency = 50 MSPS; Signal Frequency = 10 MHz; Positive peak: 0.78 lsb; Negative peak: -0.73 lsb Clock Frequency = 50 MSPS; Signal Frequency = 10 MHz; Positive peak: 0.3 lsb; Negative peak: -0.39 lsb TS8388B 17 ...
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... Effective Number Figure 8. Effective Number of Bits = Bits Versus Power Supplies Variation Figure 9. Effective Number of Bits = f (V Figure 10. Effective Number of Bits = f (V TS8388B 18 EEA -6 3.5 4 4.5 EED ...
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... Typical FFT Results Figure 11 GSPS MHz S IN Figure 12 GSPS 495 MHz S IN Figure 13 GSPS 995 MHz (-3 dB Full Scale Input 2144C–BDC–04/03 TS8388B 19 ...
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... Amplitude Figure 14. Sampling Frequency: F SINAD = 40 dB; SNR = 44 dB; THD = -46 dBc; SFDR = -47 dBc; Gray or Binary Output Coding Figure 15. Sampling Frequency: F SINAD = 40.8 dB; SNR = 44 dB; THD = -48 dBc; SFDR = -50 dBc; Gray or Binary Output Coding TS8388B GSPS; Input Frequency F = 995 MHz; Full Scale; ENOB = 6. GSPS ...
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... MHz, Full Scale input (F IN 400 600 800 1000 Input frequency (MHz) 400 600 800 1000 Input frequency (MHz) 400 600 800 1000 Input frequency (MHz) TS8388B ), 1200 1400 1600 1800 1200 1400 1600 1800 ...
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... Sampling Clock duty cycle 50/50, Binary output coding Frequency Figure 20. SFDR (dBc) -20 -25 -30 -35 -40 -45 -50 -55 -60 0 200 TS8388B 22 = 495 MHz and Nyquist conditions (F IN 400 600 800 1000 Sampling frequency (MSPS) = 495 MHz and Nyquist conditions (F IN 400 600 800 1000 ...
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... TS8388B ADC Performances Versus Junction Temperature Figure 21. Effective Number of Bits Versus Junction Temperature GSPS 500 MHz; Duty Cycle = 50 -40 -20 Figure 22. Signal to Noise Ratio Versus Junction Temperature GSPS 507 MHz; Differential Clock; Single-ended Analog Input ( ...
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... Typical Full Power Input Bandwidth Figure 25. 1.8 GHz (-2 dBm Full Power Input) – CBGA68 package 400 600 TS8388B Temperature (°C) Frequency (MHz) 800 1000 1200 1400 100 120 140 160 1600 ...
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... Figure 26. 1.5 GHz (-2 dBm Full Power Input) – CQFP68 package 100 300 2144C–BDC–04/03 Frequency (MHz) 500 700 900 1100 TS8388B 1300 1500 1700 25 ...
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... ADC Step Test pulse input characteristics: 20% to 80% input full scale and rise time ~ 200 ps. Response Note: Figure 27. Test Pulse Digitized with 20 GHz DSO 0 0.5 1.0 Figure 28. Same Test Pulse Digitized with TS8388B ADC 200 150 100 0.5 1.0 Note: Ripples are due to the test setup (they are present on both measurements). ...
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... TS8388B Main Features Timing Information Timing Value for Timing values as defined in Table 3 on page 4 are advanced data, issued from electric simula- TS8388B tions and first characterizations results fitted with measurements. Timing values are given at package inputs/outputs, taking into account package internal con- trolled impedance traces propagation delays, gullwing pin model, and specified termination loads ...
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... TRDR is measured between the -1.3V point of the falling edge of DRRB input command and the zero crossing point of the differential Data Ready output signal (DR, DRB). The Data Ready Reset command may be a pulse minimum time width. TS8388B 28 If TOD is at 1150 ps, TDR will not be at 1620 ps (maximum time delay for TDR). ...
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... In differential mode input configuration, that means 0.25V on each input, or 0V. The input common mode is GROUND. The typical input capacitance for TS8388B in CQFP and CBGA packages. The input capacitance is mainly due to the package. The ESD protections are not connected (but present) on the inputs. ...
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... Although the clock inputs were intended to be driven differentially with nominal -0.8V/-1.8V Input (Ground ECL levels, the TS8388B clock buffer can manage a single-ended sinewave clock signal cen- Common Mode) tered around 0V. This is the most convenient clock input configuration as it does not require the use of a power splitter ...
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... Ground reference for the inphase clock input. Thus the TS8388B differential clock input buffer will fully reject the local ground noise (and any capacitively and inductively coupled noise) as common mode effects. Moreover, a very low phase noise sinewave generator must be used for enhanced jitter performance ...
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... Moreover, proper active signals shielding has been provided on the chip to reduce the amount of coupled noise on the active inputs. The analog inputs and clock inputs of the TS8388B device have been surrounded by ground pins, which must be directly connected to the external ground plane. Digital Outputs The TS8388B differential output buffers are internally 75 nected to the digital ground pins through a -0 ...
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... At sampling rates exceeding 1 GSPS, it may be difficult to trigger any Acquisition System with digital outputs. It becomes necessary to regenerate digital data and Data Ready by means of external amplifiers, in order to be able to test the TS8388B at its optimum performance conditions. 2144C–BDC–04/03 impedance transmission lines, 75 0.41V = 0.825V in differential, around -1.21V (respectively +1.21V) common mode for ± ...
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... Figure 34. Differential Output: 75 VPLUSD = 0V -0.8V 75Ω 75Ω DVEE Figure 35. Differential Output: 50 VPLUSD = 0V -0.8V 75Ω 75Ω DVEE TS8388B 34 Terminated 75Ω 75Ω impedance Terminated 50Ω 50Ω impedance Out -1V/-1.41V 75Ω Differential output: +0.41V = 0.825V Common mode level: -1.2V (-1.2V below VPLUSD level) 75Ω ...
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... VPLUSD = 2.4V 1.6V 75Ω 75Ω DVEE 2144C–BDC–04/03 75Ω 75Ω impedance Terminated 75Ω 75Ω impedance TS8388B Out -0.8V/-1.6V Differential output: +0.8V = 1.6V Common mode level: -1.2V (-1.2V below VPLUSD level) OutB -1.6V/-0.8V Out 1.4V/0.99V 75Ω Differential output: +0.41V = 0.825V Common mode level: -1.2V (-1.2V below VPLUSD level) 75Ω ...
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... This is due to the fact that the latches are regenerating the internal analog residues into logical states with a finite voltage gain value (Av) within a given positive amount of time (t exp( (t)/ ), with the positive feedback regeneration time constant. The TS8388B has been designed for reducing the probability of occurrence of such errors to approximately 10 TS8388B ...
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... A standard technique for reducing the amplitude of such errors down to putting the digital datas in Gray code format. Though the TS8388B has been designed for featuring a Bit Error Rate of 10 select between the Binary or Gray output data format, in order to reduce the amplitude of such errors when occurring, by storing Gray output codes ...
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... Figure 41. ADC Gain Control Pin 60 Note: TS8388B 38 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 -500 -400 -300 -200 -100 Vgain (command voltage) (mV) For more information, please refer to the document "DEMUX and ADCs Application Notes". 0 100 200 300 400 500 2144C–BDC–04/03 ...
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... E31V CLK Pad capacitance 340 fF 5.8V 0.8V E21G Note: The ESD protection equivalent capacitance is 150 fF. 2144C–BDC–04/03 VCLAMP = +2.4V +1.65V 200Ω -1.55V VEE = -5V +0.8V GND = 0V 150Ω VEE = -5V TS8388B VCC -0.8V GND -5.8V E21V VEE 200Ω 5.8V 0.8V E21G VCC -0.8V -5.8V -5.8V VEE E31V 150Ω 5.8V 380 µA ...
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... E21GA VEE = -5V Note: The ESD protection equivalent capacitance is 150 fF. Figure 45. ADC Gain Adjust Equivalent Analog Input Circuit and ESD Protections NP1032C2 GA Pad capacitance 180 fF Note: The ESD protection equivalent capacitance is 150 fF. TS8388B 40 VPLUSD = 0V to 2.4V -5.8V 5.8V 0.8V 0.8V DVEE = -5V VCC = +5V -0.8V -5.8V E22V 1 kΩ 0. ...
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... Pad capacitance 180 fF VEE Note: The ESD protection equivalent capacitance is 150 fF. 2144C–BDC–04/03 VCC = +5V -0.8V 1 kΩ -0.8V -5.8V E21VA 5 kΩ 5.8V 5.8V 5.8V E31G GND=0V NP1032C2 10 kΩ 200Ω -2.6V 5.8V 0.8V E21G TS8388B 1 kΩ 1 kΩ 250 µA 250 µA GND = 0V VCC = +5V -1.3V VEE = -5V 41 ...
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... Board General The TSEV8388B Evaluation Board (EB board which has been designed in order to facili- tate the evaluation and the characterization of the TS8388B device up to its 1.5 GHz full power Description bandwidth GSPS in the military temperature range. The high speed of the TS8388B requires careful attention to circuit design and layout to achieve optimal performance ...
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... This value does not include thermal contact resistance between package and external compo- Case: RTHJC nent (heatsink or PCBoard example, 2.0 C/W can be taken for 50 µm of thermal grease. 2144C–BDC–04/03 Air flow (m/s) 0 0.5 1 1 Air flow (m/s) TS8388B Estimated JA thermal resistance ( C/W) 45 35.8 30.8 27.4 24.9 23 21.5 19.3 17 ...
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... Devices require baking, before mounting, if Humidity Indicator Card is >20% when read ± baking is required, devices may be baked for: • 192 hours C/-0 C and <5% RH for low-temperature device containers, or • 24 hours at 125 C ±5 C for high temperature device containers. TS8388B 44 50.5 24.2 20.2 31 32.5 Board ...
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... Estimated – Without Heatsink 23.5 1. Heatsink is glued to backside of package or screwed and pressed with thermal grease Thermal Resistance ( C/W) CQFP68 on Board Targeted – With Heatsink 8.9 7.9 7.3 6.8 6.5 6.2 5.8 5.6 Without heatsink With heatsink Air flow (m/s) TS8388B ( ...
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... Thermal Resistance Typical value for Rthjc is given to 4.75 C/W. from Junction to Case: RTHJC CQFP68 Board Assembly Figure 51. CQFP68 Board Assembly with External Heatsink Printed circuit Aluminum heatsink Interface: Af-filled epoxy or thermal conductive grease - 100 µm max. TS8388B 46 28.96 24.13 15.0 1.3 3.2 50.0 1.4 4.0 2.5 16.0 2144C–BDC–04/03 ...
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... The stand off has been calculated to permit the simultaneous soldering of the leads and of the heatspreader with the solder paste. Figure 52. Enhanced CQFP68 Suggested Assembly Printed circuit board CuW heatspreader Cooling system efficiency can be monitored using the Temperature Sensing Diode, integrated in the device. 2144C–BDC–04/03 TS8388B 28.78 24.13 Thermal via Solid ground plane 47 ...
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... Peak Phase variation (in degrees) at five different DC levels for an AC signal of 20% Full Scale peak to peak amplitude. F (TA) Aperture Delay Delay between the rising edge of the differential clock inputs (CLK, CLKB) (zero crossing point), and the time at which (V TS8388B 48 4 lsb from the correct code. ± SINAD - 1. log (A/V/2) 6 ...
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... TC2 = Minimum clock pulse width (low) (TPD) Pipeline Delay Number of clock cycles between the sampling edge of an input data and the associated output data being made available, (not taking in account the TOD). For the TS8388B the TPD is 4 clock periods. (TRDR) Data Ready ...
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... Information Table 11. Ordering Information Part Number Package JTS8388B-1V1B Die JTS8388B-1V2B Die TS8388BCF CQFP 68 TS8388BVF CQFP 68 TS8388BMF CQFP 68 TS8388BMF B/Q CQFP 68 TS8388BMF B/T CQFP 68 TS8388BCFS CQFP 68 with heatspreader TS8388BVFS CQFP 68 with heatspreader TS8388BMFS CQFP 68 with heatspreader TS8388BMFS B/Q CQFP 68 with heatspreader TS8388BMFS B/T CQFP 68 with heatspreader ...
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... Standard -40 C < Tc; Tj < 110 C Ambient Prototype Ambient Prototype Ambient Prototype Ambient Prototype TS8388B Comments Evaluation board (delivered with heatsink) Evaluation board with digital receivers (delivered with heatsink) Evaluation board (delivered with heatsink) Evaluation board with digital receivers (delivered with ...
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... CBGA68 Capacitors and Resistors Implant Figure 53. TS8388BGL Capacitors and Resistors Implant ∅ 7.0 mm 0.9 mm Only on-package marking Electrically isolated Note: TS8388B 52 0.9 mm GND 100 pF DVEE VEE VCC VEE CLKB 100 pF 100 pF 100 pF 50Ω GND GND GND GND R and C are discrete components of 0603 size (1.6 x 0.8 mm). ...
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... Detail of ball Top side with soldered R, C 0.95 max devices (using solder Sn/Pb 63/37) Balls Sn/Pb 63/37 1.45 ± 0.12 1.27 ref 0.63 ± 0.10 All units in mm TS8388B Balls side AI203 substrate AI203 Ceramic Cap. Glued and embedded in substrate 53 ...
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... Outline Figure 55. Package Dimension – 68-lead Ceramic Quad Flat Pack (CQFP) Dimensions TS8388B 54 TOP VIEW 0.8 BCS 20.32 BSC 0.050 BCS Pin N° 1 index 1.27 BSC CQFP 68 0.950 ± 0.006 24.13 ± 0.152 1.133 - 1.147 28.78 - 29.13 0.027 - 0.037 0.70 - 0.95 0.005 - 0.010 0.13 - 0.25 2144C–BDC–04/03 ...
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... Figure 56. Package Dimension – 68-lead Enhanced CQFP with Heatspreder 2144C–BDC–04/03 TOP VIEW 0.8 BCS 20.32 BSC 0.050 BCS Pin N° 1 index 1.27 BSC CQFP 68 0.950 ± 0.006 24.13 ± 0.152 1.133 - 1.147 28.78 - 29.13 0.027 - 0.037 0.70 - 0.95 TS8388B 0.005 - 0.010 0.13 - 0.25 55 ...
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... Atmel Applications customers using or selling these products for use in such applications their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale. TS8388B 56 This datasheet contains target and goal specifications for discussion with customer and application validation ...
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... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...