NJU7085 JRC, NJU7085 Datasheet - Page 9

• Manufacturer Part Number: NJU7085
• Description: Audio Amplifier / SSOP32
• Manufacturer: JRC

www.DataSheet4U.com
1.
1.1 The NJU7085 may be not effective for a sound without the reverberation such as FM and monaural signal
1.2 eala Mobile mode may be not effective in the system that speaker distance is more than 20 cm. In this
1.3 NJU7085 includes RF rectification canceling circuit, but please confirm it by an enough examination in
2.Operation Outline
Fig.1 shows the block diagram of NJU7085.
It consists of eala surround block, power amp block, bias block, thermal shutdown block, control block.
The surround effect can be adjusted with eala effect volume (external resister: R2).
Two external resisters adjust the closed loop gain (Ri, Rf).
The standby function contributes to low consumption by suspecting all circuits.
Charge mode allows start time to shorten because of the external reference capacitor(C2) charged rapidly.
By using external capacitors C2, C3, The NJU7085 reduces pop noise during turn-on and turn-off transitions.
Please refer to captor 3 detail of Pop noise.
APPLICATION NOTES
Notice
amplifier with surround sound technology for cellular phones and portable equipments.
mode (surround for narrow space speaker), STBY mode (IC is non-active), charge mode (Reference
Voltage Charge mode), MUTE mode (Non output signal).
transitions.
The NJU7085 is high power (P
The external coupling capacitors are not necessary because of the differential outputs.
The closed loop gain is set 0 to 43dB by selecting the ratio of Ri to Rf.
The NJU7085 contains 6-mode:Bypass mode (Input through), eala mode (stereo surround), eala Mobile
The NJU7085 includes pop noise protection circuit eliminating noises during turn-on and turn-off
source.
case, we recommend eala mode.
your actual application.
Lch
Rch
Ci=0.1uF
Ci=0.1uF
C1=
10uF
+
V+
RIN
LIN
100k
100k
GND
22nF
C5=
Block
Bias
Vref
C2=
1uF
PS
o
ealaTC
C6=3.3nF
=400mW/ch typ.) and low operating voltage (2.8V to) stereo audio power
C3=
0.1uF
eala Processor Block
NFLO
Fig.1 Block Diagram
R9=
100k Ω
Control Block
DNC
R1=4.7k Ω
NFLI
D2
Mode Control
R2=50k Ω
R8=
100k Ω
D1
NFRI
C7=3.3nF
D0
R3=
100k Ω
ROUT
LOUT
eala
eala
Ri=20k Ω
Ri=20k Ω
RINP
LINP
Rf=20k Ω
Rf=20k Ω
ROUT-
LOUT-
ROUT+
LOUT+
NJU7085
R
R
L
L
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