BR24L16 Rohm, BR24L16 Datasheet - Page 7

• Manufacturer Part Number: BR24L16
• Description: 2k8 bit electrically erasable PROM
• Manufacturer: Rohm

Memory ICs
SDA
SDA
SCL
SCL
WP
WP
WP timing
For the WRITE operation, WP must be “LOW” during the period of time from the rising edge of the clock which takes in
D0 of first byte until the end of t
During this period, WRITE operation is canceled by setting WP “HIGH”. ( See Fig.6 (b) )
In the case of setting WP “HIGH” during t
address is not guaranteed. Please write correct data again in the case.
D1
D1
DATA (1)
DATA (1)
t
SU : WP
D0
D0
ACK
ACK
WR
Fig.6(b) WP TIMING OF THE WRITE CANCEL OPERATION
. ( See Fig.6 (a) )
Fig.6(a) WP TIMING OF THE WRITE OPERATION
BR24L16-W / BR24L16F-W / BR24L16FJ-W /
WR
t
HIGH : WP
, WRITE operation is stopped in the middle and the data of accessing
DATA (n)
DATA (n)
BR24L16FV-W / BR24L16FVM-W
ACK
ACK
STOP BIT
t
WR
t
HD : WP
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