MT8977 Mitel Networks Corporation, MT8977 Datasheet - Page 3

• Manufacturer Part Number: MT8977
• Description: ISO-CMOS ST-BUS FAMILY T1/ESF Framer Circuit
• Manufacturer: Mitel Networks Corporation

Pin Description (Continued)
Preliminary Information
DIP
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin #
PLCC
18,
19
20
22
23
24
26
27
28
29
34
37
38
39
40
42
44
6,
1
RxFDLClk
RxFDL
Name
CSTi0
E8Ko
CSTo
TxSF
RxSF
C1.5i
DSTi
E1.5i
XCtl
V
V
XSt
C2i
F0i
IC
DD
SS
Control ST-BUS Input #0. A 2048 kbit/s serial control stream that contains 24 per
channel control words and two master control words.
Extracted 8 kHz Output. The E1.5i clock is internally divided by 193 to produce an
8 kHz clock which is aligned with the received DS1 frame and output at this pin. The
8 kHz signal is derived from C1.5 in Digital Loopback mode.
System Ground.
External Control (Output). This is an uncommitted external output pin which is set
or reset via bit 3 in Master Control Word 1 on CSTi0. The state of XCtl is updated
once per frame.
External Status (Schmitt Trigger Input). The state of this pin is sampled once per
frame and the status is reported in bit 5 of Master Status Word 2 on CSTo.
Control ST-BUS Output. This is a 2048 kbit/s serial control stream which provides
the 24 per-channel status words, and two master status words.
Receive Facility Data Link Clock (Output). A 4 kHz clock signal used to clock out
FDL information. The data is clocked out on the rising edge of RxFDLClk.
Data ST-BUS Input. This pin accepts a 2048 kbit/s serial stream which contains the
24 PCM or data channels to be transmitted on the T1 trunk.
Received Facility Data Link (Output). A 4 kHz serial output stream that is
demultiplexed from the FDL in ESF mode, or the received Fs bit pattern in SLC-96
mode. It is clocked out on the rising edge of RxFDLClk.
2.048 MHz Clock Input. This is the master clock used for clocking serial data into
DSTi, CSTi0 and CSTi1. It is also used to clock serial data out of CSTo and DSTo.
Transmit Superframe Pulse Input. A low going pulse applied at this pin will make
the next transmit frame the first frame of a superframe. The device will free run if
this pin is held high.
Received Superframe Pulse Output. A pulse output on this pin designates that the
next frame of data on the ST-BUS is from frame 1 of the received superframe. The
period is 12 frames long in D3/D4 modes and 24 frames in ESF mode. Pulses are
output only when the device is synchronized to the received DS1 signal.
1.544 MHz Clock Input. This is the DS1 transmit clock and is used to output data on
TxA and TxB. It must be phase-locked to C2i. Data is clocked out on the rising
edge of C1.5i.
1.544 MHz Extracted Clock (Input). This clock which is extracted from the received
data is used to clock in data at RxA, RxB and RxD . The falling edge of the clock
is nominally aligned with the center of the received bit on RxD, RxA and RxB.
Frame Pulse Input. This is the frame synchronization signal which defines the
beginning of the 32 channel ST-BUS frame.
Internal Connection. Tied to V
Positive Power Supply Input. +5V 5%.
SS
for normal operation
Description
ISO-CMOS
.
MT8977
4-101