MT91L62 MITEL, MT91L62 Datasheet - Page 5

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MT91L62

Manufacturer Part Number
MT91L62
Description
3 Volt Single Rail Codec
Manufacturer
MITEL
Datasheet
Advance Information
Dout, on the rising edge of BCL during the time slot
defined by the STB input. Dout is tri-stated at all
times when STB is not true. If STB is valid, then quiet
code will be transmitted on Dout during the valid
strobe period. There is no frame delay through the
PCM serial circuit for synchronous operation.
For asynchronous operation Dout and Din are as
defined for synchronous operation except that the
allowed output jitter on Dout is larger. This is due to
the resynchronization circuitry activity and will not
affect operation since the bit cell period at 128 kb/s
and 256 kb/s is relatively large. There is a one frame
delay
asynchronous operation. Refer to the specifications
of Figures 5 & 6 for both synchronous and
asynchronous SSI timing.
PWRST
While the MT91L62 is held in PWRST no device
control or functionality is possible.
+3V
through
the
100k
100k
100k
100k
100k
1k
1k
100k
1k
100k
1k
1k
1k
0.1 F
0.1 F
0.1 F
PCM
CS0
CS1
CS2
RxMUTE
TxMUTE
serial
A/
VBias
Figure 4 - Line Card Application
circuit
10
1
2
3
4
5
6
7
8
9
for
MT91L62
Applications
Figure 4 shows an application of the MT91L62 in a
line card.
20
19
18
17
16
15
14
13
12
11
+3V
Timing
Input from Subscriber
Block
Line Interface
Din
Dout
Frame Pulse
Clock
Output to Subscriber
Line Interface
MT91L62
7-177

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