MT90823 Zarlink Semiconductor, MT90823 Datasheet - Page 11

• Manufacturer Part Number: MT90823
• Description: 3V Large Digital Switch
• Manufacturer: Zarlink Semiconductor

Data Sheet
Delay Through the MT90823
The switching of information from the input serial streams to the output serial streams results in a throughput delay.
The device can be programmed to perform time-slot interchange functions with different throughput delay
capabilities on a per-channel basis. For voice application, select variable throughput delay to ensure minimum
delay between input and output data. In wideband data applications, select constant throughput delay to maintain
the frame integrity of the information through the switch.
The delay through the device varies according to the type of throughput delay selected in the V/C bit of the
connection memory.
Variable Delay Mode (V/C bit = 0)
The delay in this mode is dependent only on the combination of source and destination channels. It is independent
of input and output streams. The minimum delay achievable in the MT90823 is three time-slots. When the input
channel data is switched to the same output channel (channel n, frame p), it will be output in the following frame
(channel n, frame p+1). The same frame delay occurs if the input channel n is switched to output channel n+1 or
n+2. When input channel n is switched to output channel n+3, n+4,..., the new output data will appear in the same
frame. Table 2 shows the possible delays for the MT90823 in the variable delay mode.
Constant Delay Mode (V/C bit = 1)
In this mode, frame integrity is maintained in all switching configurations by using a multiple data memory buffer.
Input channel data written into the data memory buffers during frame n will be read out during frame n+2.
In the MT90823, the minimum throughput delay achievable in the constant delay mode is one frame. For example,
in 2 Mb/s mode, when input time-slot 31 is switched to output time-slot 0. The maximum delay of 94 time-slots
occurs when time-slot 0 in a frame is switched to time-slot 31 in the frame. See Table 3.
Microprocessor Interface
The MT90823 provides a parallel microprocessor interface for non-multiplexed or multiplexed bus structures. This
interface is compatible with Motorola non-multiplexed and multiplexed buses.
If the IM pin is low, the MT90823 microprocessor interface assumes Motorola non-multiplexed bus mode. If the IM
pin is high, the device micro- processor interface accepts two different timing modes (mode1 and mode2) which
allows direct connection to multiplexed microprocessors.
The microprocessor interface automatically identifies the type of microprocessor bus connected to the MT90823.
This circuit uses the level of the DS/RD input pin at the rising edge of AS/ALE to identify the appropriate bus timing
connected to the MT90823. If DS/RD is high at the falling edge of AS/ALE, then the mode 1 multiplexed timing is
selected. If DS/RD is low at the falling edge of AS/ALE, then the mode 2 multiplexed bus timing is selected.
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Input Rate
128 - (n-m) time-slots
32 - (n-m) time-slots
64 - (n-m) time-slots
Table 2 - Variable Throughput Delay Value
m < n
Zarlink Semiconductor Inc.
Delay for Variable Throughput Delay Mode
(m - output channel number)
(n - input channel number))
m-n + 128 time-slots
m-n + 32 time-slots
m-n + 64 time-slots
m = n, n+1, n+2
m-n time-slots
m-n time-slots
m-n time-slots
m > n+2
MT90823
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