MT9080B Mitel Networks Corporation, MT9080B Datasheet
MT9080B
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MT9080B Summary of contents
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... ME DS5140 MT9080BP Description The MT9080B is a flexible memory module suitable for use as a basic building block in the construction of customized digital switching matrices. It can be configured as either a Data Memory or a Connection Memory, and is designed to interface with Mitel’s MT9085B. Interface to the device is via 16 bit wide data and address busses ...
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... MT9080B CMOS D8i 12 D9i D10i 14 D11i VSS 16 D12i D13i 18 D14i 20 D15i VSS CK 22 VDD 24 VSS R/W 30 DTA NC 32 Pin Description Pin # Name 1 V Ground. SS 2-5 D0i-D3i Input/Microport Data Bus. This is part bit data bus. The data bus is bidirectional in Connect Memory mode where it is typically interfaced to a microprocessor ...
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... Mode Y. See description for pin 37 Mode Z. See description for pin 37 Connection. 41 Internal Connection. Leave open for normal operation Ground Supply Voltage. +5V Connection. Description in these modes. In counter and external modes, the state of R/W pin is DD MT9080B CMOS 2-103 ...
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... MT9080B CMOS Pin Description Pin # Name 46-61 A0-A15 Address Bus. These inputs have three different functions. Inputs A0-A10 are used to address internal memory locations during read or write operations in all modes except Shift Register mode. In Shift Register mode, the levels latched in on A0-A10 program the delay through the device ...
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... CM-2 clocked into the device in the current frame will be CNT clocked out in the next frame. If the difference is EXT greater than or equal to two channels, data will be SR clocked out in the same frame. DM-3 further illustrated in Figure 5. MT9080B CMOS CK FP Data Output D0 -D15 -D15 o o ...
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... MT9080B CMOS CK External CH X Address Bus A0-A15 Data Output D0-D15o FP Address generated by 1022 Internal 11 Bit Counter Data Input D0-D15i Data is clocked out of the memory location addressed by external address bus. The address is latched in with CK edge marked . Data is clocked out with CK edge marked Data is latched into the device with the last rising edge the timeslot (e ...
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... Internal memory locations can be randomly accessed via the microprocessor bus. The pinout of the device in this mode is illustrated in Figure 7. FRAME 1 1023 1 Written to Block 0 FRAME 1 1 1023 Read from Block 1 MT9080B CMOS Number of channels in the switching matrix 2,048 1,024 512 ...
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... MT9080B CMOS CK 16 D0-D15 A0-A15 CS DS R/W DTA 0/1 Figure 7 - Connect Memory Modes Pinout Data is clocked out on D0 -D15 o locations addressed sequentially by the internal counter. This counter is incremented every second clock period and is reset with FP. The frequency of the clock signal used should be twice the data rate. ...
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... Maximum permissible delay is equal to 4096 clock cycles. The pertinent timing parameters are illustrated in Figure 14. Data is clocked in and out of the device with rising edge of the clock. The address is latched in with the negative edge of DS while the CS is low. MT9080B CMOS -D15 -D15 ...
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... MT9080B CMOS CK FP Data Data Out Figure 14 - Shift Register Mode Data Input/Output Timing Applications 1024 Channel Switch Matrix A 1024 channel, non-blocking, timeslot interchange switch can be constructed using two SMX devices (refer to Figure 15). One SMX is operated in the Data Memory mode, while the second device is operated in Connect Memory Mode-1 ...
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... -D9 D10 D11 D12 SMX #2 CM-1 FP CONNECTION MEMORY CD D0-D15 R/W DTA DS D0-D15 R/W HALT DS 16-BIT MPU IRQ MT9080B CMOS This bit will be -D15 Parallel Output Data A10-A15 +5 R External Tristate Control D13 MODE A11-A15 +5 ...
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... MT9080B CMOS CK CONNECTION MEMORY TIMING FP #2 Internal Counter 1023 0 (Read Address) addresses Data Output 1022 1023 D0o-D15o DATA MEMORY TIMING Data Output 1021 D0o-D15o FP #1 Internal Counter (Write Address) Data In 1021 D0i-D15i Note 1: Address is latched into the Data Memory by the first positive clock edge in a timeslot (edge ...
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... CNT/EXT SMX # D0-D15o +5 Mx C16 DATA My MEMORY CS DS A0-A10 D11 D0o-D10o CM-2 SMX #3 CONNECTION FP MEMORY CK C16 MPU Interface ). SS MT9080B CMOS channel, double buffered CNT/EXT SMX #2 16 D0-D15o D0-D15i + DATA My FP MEMORY R/W ODE A0-A10 ODE ...
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... MT9080B CMOS CK DFP (SMX #1) DFP (SMX #2) Written to SMX #2 Data In 2045 2046 2047 (SMX1/2) CFP (SMX #3) SMX #3 2046 2047 0 Int. Counter SMX #3 2045 2046 2047 D0o-D10o Read from SMX #1 Data Out 2044 2045 (SMX 1/2) Figure 19 - 2048 Channel Switch Timing LARGE MATRIX 1 Data ...
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... SMX. The data output bus of the third SMX is connected to the data bus of the MPU. the greater Data in SMX #3 MESSAGING DM D15 16 i ADDR Figure 1024 Channel Switch Matrix with Message Capability MT9080B CMOS CK FP DM-1/DM-2 +5V ODE D0-D15o 16 A0-A11 DS DTA CD R/W +5V D0-D15 Microprocessor SMX #1 ...
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... MT9080B CMOS Parallel-to-Serial Conversion The SMX can be used in systems which employ serial architectures by converting the parallel I/O into a serial format. The Mitel MT9085 Parallel Access Circuit (PAC) is designed to interface to the parallel busses of the SMX. A single PAC can convert the output of a1024 channel switch into 2.048 Mbit/s or 4.096 Mbit/s serial format. A second PAC can be confi ...
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... MT9080B CMOS Min Max Units -0 -0 -0 -40 125 150 unless otherwise stated. SS Units Test Conditions Units Test Conditions ...
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... MT9080B CMOS AC Electrical Characteristics . to Ground (V ) unless otherwise stated SS Characteristics 1 ODE Setup 2 ODE Hold 3 Data Output High Z to Active 4 Data Output Active to High Z † Timing is over recommended temperature and power supply voltages. ‡ Typical figures are and are for design aid only; not guaranteed and not subject to production testing. ...
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... External, Connect Memory-2 and Counter Mode Timing ) unless otherwise stated. SS ‡ Sym Min Typ Max t 10 WEH t 2 WES MES t 26 MEH MT9080B CMOS Units Test Conditions MEH t MES Units ...
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... MT9080B CMOS CK A0-A15*, R/W** t WES ME/Mx/y/z t MES D0i-D15i D0o-D15o * Timing applicable to External mode only. ** Timing applicable to External and Counter modes. Figure 26 - External, Connect Memory-2 and Counter Mode Timing AC Electrical Characteristics Voltages are with respect to Ground (V ) unless otherwise stated. SS Characteristics 1 Address Setup 2 Address Hold ...
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... CSH 4.5 DTAD t 0 DTAH DHZ t CSS DTAD t RD External Mode MT9080B CMOS ) unless otherwise stated. SS Max Units Test Conditions CSH DTAH t DHZ t DH ...
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... MT9080B CMOS AC Electrical Characteristics (See Fig. 29) - Voltages are with respect to Ground (V Characteristics 1 Chip Select Setup 2 Chip Select Hold 3 ADDR, R/W Setup 4 ADDR, R/W Hold 5 DTA Delay 6 DTA Hold 7 DS Low to Data in Delay 8 DTA Low to Data in Hold 9 DS Hold Time * T = Clock (CK) Period CK † Timing is over recommended temperature and power supply voltages. ...
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... Figure 30 - Frame Pulse and Change Detect Timing † - Frame Pulse, Clock and Change Detect Timing (See Fig. ) unless otherwise stated. SS ‡ Sym Min Typ Max t 6 FPS t 3 FPH t 38 CDD CDRD t t FPS FPH t CDD* MT9080B CMOS Units Test Conditions CDRD 2-123 ...
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Package Outlines Dim D General- (lead coplanarity) A Notes Not ...
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