MT5C1009 ASI, MT5C1009 Datasheet - Page 5

no-image

MT5C1009

Manufacturer Part Number
MT5C1009
Description
128K x 8 SRAM WITH CHIP & OUTPUT ENABLE
Manufacturer
ASI
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT5C1009C-25L
Manufacturer:
a
Quantity:
27
Part Number:
MT5C1009C-35/883C
Manufacturer:
MOT
Quantity:
780
Part Number:
MT5C1009C-45883C
Manufacturer:
a
Quantity:
20
Part Number:
MT5C1009C-55L
Manufacturer:
MOT
Quantity:
650
NOTES
1.
2.
3.
4.
5.
6.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
* Low Power, -20 device only
V
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
CC
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
All voltages referenced to V
-2V for pulse width < 20ns
I
The specified value applies with the outputs
unloaded, and f =
This parameter is guaranteed but not tested.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
t
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
allowing for actual tester RC time constant.
LZCE,
CC
for Retention Data
DESCRIPTION
is dependent on output loading and cycle rates.
t
LZWE,
CE1\
t
LZOE,
V
t
RC (MIN)
CC
1
V
V
t
IL
IH
HZCE,
1 2 3 4 5 6 7 8 9
1 2 3
1 2 3 4
1 2 3 4 5 6 7 8 9
1 2 3
1 2 3 4
1 2 3 4 5 6 7 8 9
1 2 3
1 2 3 4
1 2 3 4 5 6 7 8 9
1 2 3
1 2 3 4
1 2 3 4 5 6 7 8 9
1 2 3
SS
Hz.
CE\ > (V
(GND).
V
LOW Vcc DATA RETENTION WAVEFORM
IN
t
HZOE and
> (V
or < 0.2V
CONDITIONS
t
CC
CC
CDR
- 0.2V)
- 0.2V)
t
HZWE
4.5V
DATA RETENTION MODE
V
CC
V
V
DR
DR
= 2V
7.
8.
9.
10. Address valid prior to, or coincident with, latest
11.
> 2V
Q
255
At any given temperature and voltage condition,
t
t
WE\ is HIGH for READ cycle.
Device is continuously selected. Chip enables and
output enables are held in their active state.
occurring chip enable.
t
HZCE is less than
LZWE and
RC = Read Cycle Time.
Fig. 1 Output Load
SYMBOL
I
I
CCDR1
CCDR2
Equivalent
t
V
CDR
t
DR
R
4.5V
*
t
HZOE is less than
+5V
MIN
t
t
R
t
RC
LZCE, and
2
0
480
30
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Q
MAX
0.75
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1.0
255
---
---
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
t
t
LZOE.
HZWE is less than
MT5C1009
Fig. 2 Output Load
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
UNITS NOTES
mA
mA
ns
ns
Equivalent
V
UNDEFINED
DON’T CARE
+5V
4, 11
480
5 pF
4

Related parts for MT5C1009