XC2S100E-6FG456I Xilinx, XC2S100E-6FG456I Datasheet - Page 2

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XC2S100E-6FG456I

Manufacturer Part Number
XC2S100E-6FG456I
Description
Spartan-IIE 1.8V FPGA Family
Manufacturer
Xilinx
Datasheet

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Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information
General Overview
The Spartan-IIE family of FPGAs have a regular, flexible,
programmable architecture of Configurable Logic Blocks
(CLBs), surrounded by a perimeter of programmable
Input/Output Blocks (IOBs). There are four Delay-Locked
Loops (DLLs), one at each corner of the die. Two columns
of block RAM lie on opposite sides of the die, between the
CLBs and the IOB columns. These functional elements are
interconnected by a powerful hierarchy of versatile routing
channels (see
Spartan-IIE FPGAs are customized by loading configura-
tion data into internal static memory cells. Unlimited repro-
gramming cycles are possible with this approach. Stored
values in these cells determine logic functions and intercon-
nections implemented in the FPGA. Configuration data can
be read from an external serial PROM (master serial mode),
or written into the FPGA in slave serial, slave parallel, or
Boundary Scan modes. The Xilinx XC17S00A PROM family
is recommended for serial configuration of Spartan-IIE
FPGAs. The XC18V00 reprogrammable PROM family is
recommended for parallel or serial configuration.
Spartan-IIE FPGAs are typically used in high-volume appli-
cations where the versatility of a fast programmable solution
adds benefits. Spartan-IIE FPGAs are ideal for shortening
product development cycles while offering a cost-effective
solution for high volume production.
2
Figure
1).
I/O LOGIC
DLL
DLL
Figure 1: Basic Spartan-IIE Family FPGA Block Diagram
www.xilinx.com
1-800-255-7778
Spartan-IIE FPGAs achieve high-performance, low-cost
operation through advanced architecture and semiconduc-
tor technology. Spartan-IIE devices provide system clock
rates beyond 200 MHz. Spartan-IIE FPGAs offer the most
cost-effective solution while maintaining leading edge per-
formance. In addition to the conventional benefits of
high-volume programmable logic solutions, Spartan-IIE
FPGAs also offer on-chip synchronous single-port and
dual-port RAM (block and distributed form), DLL clock driv-
ers, programmable set and reset on all flip-flops, fast carry
logic, and many other features.
Spartan-IIE Family Compared to Spartan-II
Family
Higher density and more I/O
Higher performance
Unique pinouts in cost-effective packages
Differential signaling
-
V
-
-
-
PCI, LVTTL, and LVCMOS2 input buffers powered by
V
Unique larger bitstream
CCINT
CCO
LVDS, Bus LVDS, LVPECL
Lower power
5V tolerance with 100
3V tolerance directly
instead of V
= 1.8V
CCINT
DLL
DLL
DS077_01_102201
Preliminary Product Specification
DS077-1 (v1.0) November 15, 2001
external resistor
R

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