S-24C01A Seiko Instruments Inc, S-24C01A Datasheet - Page 13

• Manufacturer Part Number: S-24C01A
• Description: CMOS 2-WIRE SERIAL EEPROM
• Manufacturer: Seiko Instruments Inc

Rev. 2.2
SDA LINE
7.3 Sequential Read
When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code "1" in
both current and random read operations, following the start condition signal, it outputs the
acknowledgment signal
When 8-bit length data is output from the EEPROM, in synchronization with the SCL clock, the memory
address counter inside the EEPROM is automatically incremented at the falling edge of the SCL clock, by
which the 8th data is output.
When the master device transmits the acknowledgment signal, the next memory address data is output.
When the master device transmits the acknowledgment signal, the memory address counter inside the
EEPROM is incremented and read data in succession. This is called "Sequential Read."
When the master device does not output an acknowledgement signal and transmits the stop condition
signal, the read operation is finished.
Data can be read in the "Sequential Read" mode in succession. When the memory address counter
reaches the last word address, it rolls over to the first memory address.
_30
ADDRES
DEVICE
W
R
E
A
D
R
1
/
A
C
K
D7
DATA (n)
D0
ADR INC
Figure 14 Sequential Read
A
C
K
D7
Seiko Instruments Inc.
DATA (n+1)
D0
ADR INC
A
C
K
D7
DATA (n+2)
CMOS 2-WIRE SERIAL EEPROM
ADR INC
D0
C
A
K
D7
Master Device
NO ACK from
S-24C01A/02A/04A
DATA (n+x)
ADR INC
D0
S
O
P
T
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