FM24C128A Shanghai Fudan Microelectronics Co., Ltd., FM24C128A Datasheet - Page 10

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FM24C128A

Manufacturer Part Number
FM24C128A
Description
2-wire Serial Eeprom
Manufacturer
Shanghai Fudan Microelectronics Co., Ltd.
Datasheet

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Figure 6.Output Acknowledge
Device Addressing
The 128K/256K EEPROM device requires a 8-bit
device address word following a start condition to
enable the chip for a read or write operation (refer
to Figure 7).
The device address word consists of a mandatory
one, zero sequence for the first four most
significant bits as shown. This is common to all the
EEPROM devices.
The 128K/256K EEPROM uses the three device
address bits A2, A1, A0 to allow as many as eight
devices on the same bus. These bits must compare
to their corresponding hard-wired input pins. The
A2, A1 and A0 pins use an internal proprietary
circuit that biases them to a logic low condition if
the pins are allowed to float.
FM24C128A/256A 2-Wire Serial EEPROM
The eighth bit of the device address is the
read/write operation select bit. A read operation is
initiated if this bit is high and a write operation is
initiated if this bit is low.
Upon a compare of the device address, the
EEPROM will output a zero. If a compare is not
made, the device will return to a standby state.
NOISE PROTECTION: Special internal circuitry
placed on the SDA and SCL pins prevent small
noise spikes from activating the device.
DATA SECURITY: The FM24C128A/256A has a
hardware data protection scheme that allows the
user to write protect the entire memory when the
WP pin is at V
Ver 1.4
CC
.
Data Sheet
10

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