S-1172 Seiko Instruments, S-1172 Datasheet - Page 14

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S-1172

Manufacturer Part Number
S-1172
Description
HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR
Manufacturer
Seiko Instruments
Datasheet

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14
HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR
S-1172 Series
Operation
1. Basic operation
2. Output transistor
Figure 13 shows the block diagram of the S-1172 Series.
The error amplifier compares the reference voltage (V
feedback resistors R
is not influenced by the input voltage and temperature change, to the output transistor.
In the S-1172 Series, a low on-resistance P-channel MOS FET is used as the output transistor.
Be sure that V
current which flows, because of a parasitic diode between the VIN and VOUT pin, when the potential of V
became higher than V
OUT
VIN
VSS
*1. Parasitic diode
does not exceed V
Current
s
supply
Reference voltage
IN
and R
.
V
ref
circuit
f
. It supplies the gate voltage necessary to maintain the constant output voltage which
IN
Error amplifier
+ 0.3 V to prevent the voltage regulator from being damaged due to inverse
+
Seiko Instruments Inc.
Figure 13
ref
) with V
fb
, which is the output voltage resistance-divided by
V
R
R
fb
f
s
*1
VOUT
Rev.1.1
_00
OUT

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