AN177 Philips, AN177 Datasheet - Page 5

• Manufacturer Part Number: AN177
• Description: An Overview og the Phase Locked Loop
• Manufacturer: Philips

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Philips Semiconductors
consideration in PLL applications utilizing counters where
waveshapes usually aren’t symmetrical; i.e., 50% duty cycle. For the
TTL family, it is easier to provide the edge matching function on the
falling edges (”l” to ”O”) transition of the waveform. CMOS, 12L, and
ECL are better suited for leading edge triggering (”O” to ”1”).
Analog PLLs utilize a phase comparator which functions as a
four-quadrant analog multiplier to mix the input and VCO signals.
Since this mixing is true analog multiplication, the phase
comparator’s output is a function of input and VCO signal
amplitudes, frequencies, phase relationships, and duty cycles. The
inherent linearity afforded by this analog multiplication makes the
monolithic analog PLL well suited for many general purpose and
communication system applications.
Another way of distinguishing between digital and analog phase
comparators is by thinking of the similarities and differences
between voltage comparators and operational amplifiers. Voltage
comparators are specially designed for digital applications where
response time between output levels has been minimized at the
expense of system linearity. Feedback is seldom used to maintain
linear system relationships, with the comparator normally running
open-loop. Op amps, on the other hand, are designed for a linear
inputoutput relationship, with negative feedback being employed to
further improve the system linearity.
PLL TERMINOLOGY
The following is a brief glossary of frequently encountered terms in
PLL literature.
Free-running Frequency (f
frequency, this is the frequency at which the loop VCO operates
when not locked to an input signal. The ”prime” superscripts are
used to distinguish the free-running frequency from f
are used for the general oscillator frequency. (Many references use
f
and leave the proper choice for the reader to infer from the context.)
The appropriate units for f
respectively.
Lock Range (2f
loop will remain in lock. Normally the lock range is centered at the
free-running frequency, unless there is some nonlinearity in the
system which limits the frequency deviation on one side of f
deviations from f
Range . (See Figure 6). The tracking range is therefore one-half of
the lock range.
Capture Range (2f
throughout its lock range, it may not be able to acquire lock at the
tracking range extremes because of the selectivity afforded by the
low-pass filter. The capture range also is centered at f
equal deviations called the Lock-in or Pull-in Ranges . The capture
range can never exceed the lock range.
Lock-up Time (t
free-running loop to lock. This time depends principally upon the
bandwidth selectivity designed into the loop with the lowpass filter.
The lock-up time is inversely proportional to the selectivity
bandwidth. Also, lock-up time exhibits a statistical spreading due to
random initial phase relationships between the input and oscillator
phases.
Phase Comparator Converslon Gain (K
constant relating the phase comparator’s output voltage to the
phase difference between input and VCO signals when the loop is
December 1988
O
An overview of the phase-locked loop (PLL)
and
O
for both the free-running and general oscillator frequency
L
O
L
, 2
’ are referred to as the Tracking Range or Hold-in
)*** — The transient time required for a
C
, 2
L
)* — The range of frequencies over which the
C
O
)** — Although the loop will remain in lock
’ and
O
’,
O
’) — Also called the center
O
’ are Hz and radians per second,
d
) — The conversion
O
O
and
’ with the
O
O
’. The
which
5
locked. At low input signal levels, K
amplitude. K
VCO Conversion Gain (K
the oscillator’s frequency shift from f
K
linear function of
provided or experimentally measured at the desired
Loop Gain (K
gain at DC. K
K
Closed-Loop Gain (CLG) — The output signal frequency and
phase can be determined from a product of the CLG and the input
signal where the CLG is given by
Natural Frequency (
determined mathematically by the final pole positions in the complex
plane or determined experimentally as the modulation frequency for
which an underdamped loop gives the maximum frequency
deviation from f
Damping Factor ( ) — The standard damping constant of a second
order feedback system. For the PLL, refers to the ability of the
loop to respond quickly to an input frequency step without excessive
overshoot.
Loop Noise Bandwidth (B
which describes the effective bandwidth of the received signal.
Noise and signal components outside this bandwidth are greatly
attenuated.
REFERENCES
1. Appleton, E.V., ”Automatic Synchronization of Triode Oscillators”,
2. Gardner, F.M., Phaselock Techniques , New York: Wiley, 1966.
3. Blanchard, A., Phase-Locked Loops , New York: Wiley, 1976.
4. Viterbi, A.J., Principles of Coherent Communications , New York:
5. Connelly, J.A., Analog Integrated Circuits: Devices, Circuits,
O
O
L1
Proc. Cambridge Phil. Soc. , vol. 2, pt. Ill, p.231, 1922 –1923.
McGraw-Hill, 1966.
Systems, and Applications , New York: Wiley, 1975.
has units of radians per second per volt (rad/sec/V). K
at the appropriate
CLG
TRACKING RANGE
Figure 6. Lock and Capture Range Relationships
C1
1
d
LOCK-IN RANGE
has units of volts per radian (V/ rad).
V
d
K
) — The product of K
O
L
is evaluated at the appropriate input signal level and
V
K
’ and at which the phase error swing is the greatest.
FREE-RUNNING FREQUENCY
V
O
C
’ and must be obtained using a formula or graph
CAPTURE RANGE
n
LOCK RANGE
O
) — The characteristic frequency of the loop,
’. K
2
2
O
L
O
) — The conversion constant relating
L
C
) — A loop property relating
V
LOCK-IN RANGE
has units of (sec)
TRACKING RANGE
d
O
C
d
is also a function of signal
’ to the applied input voltage.
, K
O
L
, and the low-pass filters
C2
–1
.
Application note
AN177
L2
O
’.
RADAN
FREQUENCY
(RAD/SEC)
O
n
is a
and
SL01010
(4)