AN1116 ST Microelectronics, AN1116 Datasheet - Page 2

• Manufacturer Part Number: AN1116
• Description: CHANGING FROM THE ST95P08 TO THE M95080 IN YOUR APPLICATION USING A SIMPLE SOFTWARE RECOGNITION METHOD
• Manufacturer: ST Microelectronics

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AN1116 - APPLICATION NOTE
The W feature
Both the ST95P08 and M95080 support the software protection mode using the BP1 and BP0 status reg-
ister bits. However, their behaviors are different with the use of the W pin.
On the ST95P08, the W pin controls the write access to the memory array:
On the M95080, the W pin provides hardware write protection of the status register (SR), except for the
WIP and WEL bits. When bit 7 (SRWD, the Status Register Write Disable bit) of the status register is ‘0’
(the initial delivery state), it is possible to write to the status register once the WEL (Write Enable Latch)
has been set, and regardless of the status of pin W (high or low).
Once bit 7 (SRWD) of the status register has been set to ‘1’, the possibility to rewrite the SR depends on
the logical level present at pin W:
– If W pin is high, it is possible to write to the status register after setting the WEL (Write Enable Latch).
– If W pin is low, any attempt to modify the status register is ignored by the device, even if the WEL is
It is possible to enter the Hardware Protected Mode (HPM) by setting the SRWD bit after pulling down the
W pin, or by pulling down the W pin after setting SRWD bit.
The only way to return from the Hardware Protected Mode, once entered, is to pull the W pin high.
If the W pin is permanently tied high, the Hardware Protected Mode cannot be activated, and the Memory
only allows the user to software-protect a part of the memory using the BPn bits of the status register. The
protection features of the device are summarized in Table 2.
Table 2. Write Protection Control on the M95080
Instruction code
Using the two standard address bytes, M95080 instructions take the following format:
(where I
The ST95P08, on the other hand, does not support the standard two byte addressing mode for high den-
sities. Instead, the A8 and A9 address bits are placed beside the instruction bits, according to the following
format:
2/4
W
W=1: write enabled throughout the entire memory array that is not software write-protected
W=0: write disabled throughout the entire memory array
set. Consequently, all the data bytes in the EEPROM area that are protected by the BPn bits of the
status register, are also hardware protected against data corruption, and become a Read Only EEP-
ROM area from the microcontroller. This mode is called the Hardware Protected Mode (HPM).
0 0 0 0 0 I
0 0 0 X
1
0
1
0
2
, I
SRWD
2
1
Bit
0
0
1
1
X
and I
2
1
I
I
1
2
I
I
0
0
1
Protected
Hardware
Protected
Software
are the instruction bits).
(SPM)
(HPM)
I
Mode
0
Hardware write protected
Writeable after setting
Status Register
WEL
Hardware write protected
Software write protected
by the BPn of the status
Protected Area
register
Data Bytes
Writeable after setting the
Writeable after setting the
Unprotected Area
WEL
WEL