AD1896 Analog Devices, AD1896 Datasheet - Page 3

• Manufacturer Part Number: AD1896
• Description: 192 kHz Stereo Asynchronous Sample Rate Converter
• Manufacturer: Analog Devices

TIMING DIAGRAMS
DIGITAL TIMING (–40 C < T
Parameter
t
f
t
t
Input Serial Port Timing
t
t
t
t
t
Output Serial Port Timing
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
Specifications subject to change without notice.
MCLKI
MCLK
MPWH
MPWL
LRIS
SIH
SIL
DIS
DIH
TDMS
TDMH
DOPD
DOH
LROS
LROH
SOH
SOL
RSTL
Refer to Timing Diagram Section.
The maximum possible sample rate is: FS
f
MCLK
of up to 34 MHz is possible under the following conditions: 0°C < T
LRCLK O
LRCLK O
SDATA O
LRCLK_I
SCLK O
SCLK O
SDATA I
TDM IN
SCLK I
1
t
DOPD
MCLK_I Period
MCLK_I Frequency
MCLK_I Pulsewidth High
MCLK_I Pulsewidth Low
LRCLK_I Setup to SCLK_I
SCLK_I Pulsewidth High
SCLK_I Pulsewidth Low
SDATA_I Setup to SCLK_I Rising Edge
SDATA_I Hold from SCLK_I Rising Edge
TDM_IN Setup to SCLK_O Falling Edge
TDM_IN Hold from SCLK_O Falling Edge
SDATA_O Propagation Delay from SCLK_O, LRCLK_O
SDATA_O Hold from SCLK_O
LRCLK_O Setup to SCLK_O (TDM Mode Only)
LRCLK_O Hold from SCLK_O (TDM Mode Only)
SCLK_O Pulsewidth High
SCLK_O Pulsewidth Low
RESET Pulsewidth LO
t
t
t
TDMS
LROS
t
LRIS
DIS
t
LROH
t
TDMH
A
t
DIH
< +105 C, VDD_CORE = 3.3 V
MAX
= f
MCLK
t
DOH
t
t
SOH
/138.
SIH
t
SOL
t
SIL
A
< 70°C, 45/55 or better MCLK_I duty cycle.
5%, VDD_IO = 5.0 V
MCLK I
RESET
Min
33.3
8
12
8
8
8
8
3
3
3
3
5
3
10
5
10%)
t
MPWH
RESET
t
RSTL
t
MPWL
Max
30.0
20
200
2, 3
AD1896
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns