AD1870 Analog Devices, AD1870 Datasheet - Page 13

• Manufacturer Part Number: AD1870
• Description: Single-Supply 16-Bit Stereo ADC
• Manufacturer: Analog Devices

Timing Parameters
For master modes, a BCLK transmitting edge (labeled “XMIT”)
will be delayed from a CLKIN rising edge by t
in Figure 17. A LRCK transition will be delayed from a BCLK
transmitting edge by t
delayed from a BCLK transmitting edge by t
falling edge will be delayed from a BCLK transmitting edge by
t
transmitting edge of BCLK by t
For slave modes, an LRCK transition must be setup to a BCLK
sampling edge (labeled “SAMPLE”) by t
and TAG outputs will be delayed from an LRCK transition by
t
BCLK transmitting edge by t
Position Controlled by WCLK Input,” WCLK must be set up
to a BCLK sampling edge by t
For both master and slave modes, BCLK must have a minimum
LO pulsewidth of t
The AD1870 CLKIN and RESET timing is shown in Figure
19. CLKIN must have a minimum LO pulsewidth of t
a minimum HI pulsewidth of t
CLKIN is given by t
pulsewidth of t
requirements for RESET.
Master Clock (CLKIN) Considerations
It is recommended that the BCLK and LRCK are derived from
CLKIN to ensure correct phase relationships. The modulator
of the AD1870 runs at 64 × f
obtained when the BCLK rate equals 64 × f
rates such as 48 × f
floor, depending on the phase relationship of BCLK to CLKIN.
DLYBWF
DLYLRDT
. The DATA and TAG outputs will be delayed from a
, and DATA and TAG outputs will be delayed from
RPWL
BPWL
S
. Note that there are no setup or hold time
CLKIN
may result in an increased spectral noise
, and a minimum HI pulsewidth of t
DLYBLR
. RESET must have a minimum LO
. A WCLK rising edge will be
DLYBDT
S
SETWBS
CPWH
, therefore best performance is
DLYDT
. The minimum period of
.
. For “Slave Mode, Data
.
SETLRBS
DLYBWR
S
or 32 × f
DLYCKB
. The DATA
, and a WCLK
, as shown
S
CPWL
. BCLK
BPWH
, and
.
Synchronizing Multiple AD1870s
Multiple AD1870s can be synchronized by making all the
AD1870s serial port slaves. This option is illustrated in Figure 6.
See the “Reset, Autocalibration, and Power Down” section for
additional information.
RESET
CLKIN
RESET
CLKIN
RESET
CLKIN
#1 AD1870
SLAVE MODE
#2 AD1870
SLAVE MODE
#N AD1870
SLAVE MODE
WCLK
WCLK
WCLK
DATA
BCLK
LRCK
DATA
BCLK
LRCK
DATA
BCLK
LRCK
SOURCE
CLOCK
AD1870