AD1848K Analog Devices, AD1848K Datasheet - Page 21

• Manufacturer Part Number: AD1848K
• Description: Parallel-Port 16-Bit SoundPort Stereo Codec
• Manufacturer: Analog Devices

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DATA AND CONTROL TRANSFERS
The AD1848K SoundPort Stereo Codec supports a DMA re-
quest/grant architecture for transferring data with the host com-
puter bus. One or two DMA channels can be supported.
Programmed I/O (PIO) mode is also supported for control reg-
ister accesses and for applications lacking DMA control. PIO
transfers can be made on one channel while the other is per-
forming DMA. Transfers to and from the AD1848K SoundPort
Codec are asynchronous relative to the internal data conversion
clock. Transfers are buffered, but the AD1848K supports no in-
ternal FIFOs. The host is responsible for providing playback
data before the next digital-to-analog conversion and removing
capture data before the next analog-to-digital conversion.
Data Ordering
The number of byte-wide transfers required depends on the
data format selected. The AD1848K is designed for “little
endian” formats in which the least significant byte (i.e., occupy-
ing the lowest memory address) gets transferred first. So 16-bit
data transfers require first transferring the least significant bits
7:0 and then transferring the most significant bits 15:8, where
bit 15 is the most significant bit in the word.
In addition, left channel data is always transferred before right
channel data with the AD1848K. The following figures should
make these requirements clear.
Figure 9. AD1848K 16-Bit Mono Data Stream Sequencing
Figure 8. AD1848K 8-Bit Stereo Data Stream Sequencing
Figure 7. AD1848K 8-Bit Mono Data Stream Sequencing
SAMPLE 6
SAMPLE 3
SAMPLE 6
SAMPLE 3
BYTE 4
BYTE 4
MONO
RIGHT
Figure 10. AD1848K 16-Bit Stereo Data
Stream Sequencing
BYTES 3 & 4
BYTES 3 & 4
SAMPLE 5
SAMPLE 3
SAMPLE 5
SAMPLE 3
MONO
RIGHT
BYTE 3
BYTE 3
MONO
LEFT
SAMPLE 4
SAMPLE 2
SAMPLE 4
SAMPLE 2
SAMPLE 3
SAMPLE 2
SAMPLE 3
SAMPLE 2
BYTE 2
BYTE 2
MONO
RIGHT
BYTES 1 & 2
BYTES 1 & 2
SAMPLE 2
SAMPLE 1
SAMPLE 1
SAMPLE 2
MONO
LEFT
BYTE 1
BYTE 1
MONO
LEFT
SAMPLE 1
SAMPLE 1
SAMPLE 1
SAMPLE 1
TIME
TIME
TIME
TIME
–21–
Control and Programmed I/O (PIO) Transfers
This simpler mode of transfers is used both for control register
accesses and programmed I/O. The 21 control and PIO data
registers cannot be accessed via DMA transfers. Playback PIO is
activated when both Playback Enable (PEN) is set and Playback
PIO (PPIO) is set. Capture PIO is activated when both Capture
Enable (CEN) is set and Capture PIO (CPIO) is set. See Fig-
ures 11 and 12 for the detailed timing of the control register/
PIO transfers. The RD and WR signals are used to define the
actual read and write cycles, respectively. The host holds CS
LO during these transfers. The DMA Capture Data Acknowl-
edge (CDAK) and Playback Data Acknowledge (PDAK) must
be held inactive, i.e., HI.
OUTPUTS
OUTPUTS
OUTPUTS
CS INPUT
RD INPUT
WR INPUT
OUTPUTS
CS INPUT
DATA7:0
OUTPUT
DATA7:0
DBEN &
OUTPUT
ADR1:0
INPUTS
CDRQ /
INPUTS
ADR1:0
INPUTS
DBDIR
Figure 12. AD1848K Control Register/PIO Write Cycle
INPUT
Figure 11. AD1848K Control Register/PIO Read Cycle
CDRQ/
DBDIR
PDRQ
CDAK
INPUT
PDRQ
DBEN
PDAK
HI
t
CSSU
t
t
SUDK1
SUDK1
t
t
ADSU
ADSU
t
RDDV
t
CSSU
t
t
t
t
WDSU
DBDL
t
DBDL
STW
STW
t
t
CSHD
CSHD
AD1848K
t
t
SUDK2
SUDK2
t
DHD1
t
t
t
DHD2
ADHD
ADHD