74ACTQ16646MTD Fairchild Semiconductor, 74ACTQ16646MTD Datasheet - Page 6

• Manufacturer Part Number: 74ACTQ16646MTD
• Description: IC TRANSCVR/REG 3ST 16B 56TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: 74ACTQr

Specifications of 74ACTQ16646MTD

• Logic Type: Transceiver, Non-Inverting
• Number Of Elements: 2
• Number Of Bits Per Element: 8
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Dc: 0736
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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C
C
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
(Note 11)
t
(Note 11)
t
(Note 11)
t
(Note 11)
t
(Note 11)
t
(Note 11)
t
(Note 11)
t
(Note 11)
t
(Note 11)
PHL
PLH
PHL
PLH
PHL
PLH
PZL
PZH
PLZ
PHZ
PZL
PZH
PLZ
PHZ
OSHL
OSLH
OSHL
OSLH
OSHL
OSLH
OST
OST
OST
Extended AC Electrical Characteristics
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH to LOW (t
LOW (t
Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 14: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 15: The Output Disable Time is dominated by the RC network (500 , 250 pF) on the output and has been excluded from the datasheet.
Capacitance
IN
PD
Symbol
Symbol
OST
).
Propagation Delay
Clock to Bus
Propagation Delay
Bus to Bus
Propagation Delay
Select to Bus
(w/An or Bn HIGH or LOW)
Enable Time
G to An/Bn
Disable Time
G to An/Bn
Enable Time
DIR to An/Bn
Disable Time
DIR to An/Bn
Pin-to-Pin Skew
Clock to Bus
Pin-to-Pin Skew
Clock to Bus
Pin-to-Pin Skew
Bus to Bus
Pin-to-Pin Skew
Bus to Bus
Pin-to-Pin Skew
Select to Bus
(w/An or Bn HIGH or LOW)
Pin-to-Pin Skew
Select to Bus
(w/An or Bn HIGH or LOW)
Pin-to-Pin Skew
Clock to Bus
Pin-to-Pin Skew
Bus to Bus
Pin-to-Pin Skew
Select to Bus
Input Capacitance
Power Dissipation Capacitance
Parameter
Parameter
OSHL
Min
4.1
4.2
4.0
4.7
3.8
4.3
5.0
4.1
3.2
3.5
4.1
4.4
2.9
3.4
), LOW to HIGH (t
16 Outputs Switching
T
6
A
Typ
4.5
95
V
C
(Note 12)
CC
40 C to 85 C
L
Typ
50 pF
OSLH
Com
), or any combination switching LOW to HIGH and/or HIGH to
Units
pF
pF
Max
10.1
10.0
10.7
10.9
12.7
11.3
11.3
13.0
10.1
8.3
9.5
9.6
8.6
9.7
1.0
1.0
1.0
1.0
1.0
1.2
2.1
1.0
2.7
V
V
CC
CC
T
A
Min
6.1
6.0
5.4
5.9
5.7
6.1
5.0V
5.0V
C
V
(Note 13)
L
(Note 14)
(Note 15)
(Note 14)
(Note 15)
CC
40 C to 85 C
250 pF
Com
Conditions
Max
14.5
14.8
13.7
13.5
14.2
15.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns