CM3202-00 California Micro Devices Corporation, CM3202-00 Datasheet - Page 8

• Manufacturer Part Number: CM3202-00
• Description: Ddr Vddq And Termination Voltage Regulator
• Manufacturer: California Micro Devices Corporation

Application Info (cont’d)
rent. The CM3202 is designed for optimal operation
from a nominal 3.3VDC bus, but can work with VIN as
high as 5V. When operating at higher VIN voltages,
attention must be given to the increased package
power dissipation and proportionally increased heat
generation.
V
such as a comparator, with little current draw. An ade-
quate V
divider of precision, matched resistors from V
ground. A small ceramic bypass capacitor can also be
added for improved noise performance.
Input and Output Capacitors
The CM3202 requires that at least a 220
capacitor be located near the V
maintain the input bus voltage during load transients.
An additional 4.7
and the GND, located as close as possible to those
pins, is recommended to ensure stability.
A minimum of a 220μF electrolytic capacitor is recom-
mended for the V
ceramic capacitor between the V
located very close to those pins, is recommended.
A minimum of a 220
mended for the V
low ESR to achieve best output transient response. SP
or OSCON capacitors provide low ESR at high fre-
quency, and thus are a good choice. In addition, place
a 4.7
GND, located very close to those pins. The total ESR
must be low enough to keep the transient within the
V
sink. An average current step of ± 0.5A requires:
Both outputs will remain stable and in regulation even
during light or no load conditions.
Adjusting VDDQ Output Voltage
The CM3202 internal bandgap reference is set at
1.25V. The V
resistor divider, R1 and R2:
© 2006 California Micro Devices Corp. All rights reserved.
8
REF
TT
ESR
window of 40mV during the transition for source to
μ
is typically routed to inputs with high impedance,
<
F ceramic capacitor between the V
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
REF
40mV
-------------- -
1A
can be created with a simple voltage
DDQ
=
μ
40mΩ
TT
F ceramic capacitor between the V
DDQ
voltage is adjustable by using a
μ
output. This capacitor should have
F, electrolytic capacitor is recom-
output. An additional 4.7μF
IN
pin for stability and to
DDQ
μ
F electrolytic
and GND,
TT
pin and
DDQ
●
to
IN
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where V
recommend that R1 and R2 not exceed 10kΩ each.
Shutdown
ADJSD also serves as a shutdown pin. When this is
pulled high (SHDN_H), both the VDDQ and the VTT
outputs tri-state and could sink/source less than 10μA.
During shutdown, the quiescent current is reduced to
less than 0.5mA, independent of output load.
It is recommended that a low leakage Schottky diode
be placed between ADJSD Pin and an external shut-
down signal to prevent interference with the ADJ pin’s
normal operation. When the diode anode is pulled low,
or left open, the CM3202 is again enabled.
Current Limit, Foldback and Over-temperature Pro-
tection
The CM3202 features internal current limiting with ther-
mal protection. During normal operation, V
the output current to approximately 2A and V
the output current to approximately ±2A. When V
current limiting into a hard short circuit, the output cur-
rent folds back to a lower level, about 1A, until the
over-current condition ends. While current limiting is
designed to prevent gross device failure, care should
be taken not to exceed the power dissipation ratings of
the package. If the junction temperature of the device
exceeds 170-°C (typical), the thermal protection cir-
cuitry triggers and tri-states both VDDQ and VTT out-
puts. Once the junction temperature has cooled to
below about 120-°C, the CM3202 returns to normal
operation.
Thermal Considerations
Typical Thermal Characteristics
The overall junction to ambient thermal resistance
(
sists of two paths in the series. The first path is the
junction to the case (
age style and the second path is case to ambient (
thermal resistance which is dependent on board lay-
out. The final operating junction temperature for any
θ
V
JA
DDQ
) for device power dissipation (P
=
ADJ
V
ADJ
●
= 1.25V. For best regulator stability, we
×
Fax: [phone]
R1
-------------------- -
R2
+
θ
R2
JC
) which is defined by the pack-
PRELIMINARY
●
www.cmd.com
D
) primarily con-
CM3202
DDQ
TT
08/16/06
limits
limits
TT
θ
CA
is
)