T15V4M08A TM tech, T15V4M08A Datasheet - Page 8

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T15V4M08A

Manufacturer Part Number
T15V4M08A
Description
512K X 8 LOW POWER CMOS STATIC RAM
Manufacturer
TM tech
Datasheet
tm
WRITE CYCLE 1 (
WRITE CYCLE 2 ( CE Controlled)
NOTES ( WRITE CYCLE ) :
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
A d d r e s s
D O U T
A d d r e s s
W E
C E
D O U T
D
I N
1. A write occurs during the overlap of a low CE , a low WE . A write begins at the lateat transition
2. tCW is measured from the later of CE going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change.
W E
D I N
C E
among CE goes low, WE going low. A write end at the earliest transition among CE going
high, WE going high. tWP is measured from the beginning of write to the end of write.
CH
TE
H i g h - Z
H i g h - Z
WE
t A S
Controlled)
t
A S
H i g h - Z
t
A W
t A W
t
t C W
C W
t W C
t W C
t WH Z
t W P
P. 8
t
W P
t
D W
H i g h - Z
t D W
Preliminary T15V4M08A
t
D H
t
W R
t D H
t WR
t O W
Publication Date: MAR. 2001
H i g h - Z
D O N ' T
U N D E F I N E D
Revision:0.A
C A R E

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