T15N1024A TM tech, T15N1024A Datasheet - Page 8
T15N1024A
Manufacturer Part Number
T15N1024A
Description
128K X 8 LOW POWER CMOS STATIC RAM
Manufacturer
TM tech
Datasheet
1.T15N1024A.pdf
(13 pages)
tm
WRITE CYCLE 1
WRITE CYCLE 2
NOTES ( WRITE CYCLE ) :
TM Technology Inc. reserves the right
to change products or specifications without notice.
A d d r e s s
A d d r e s
C E 1
C E 1
C E 2
C E 2
s
W E
D
W E
D
D
D
1. A write occurs during the overlap of a low
2. tCW is measured from the later of
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change.
o u t
o u t
I N
I N
the lateat transition among
the earliest transition among
measured from the beginning of write to the end of write.
CH
TE
(
( CE Controlled)
WE
t
Controlled)
A S
t
CE
A S
H i g h - Z
H i g h - Z
H i g h - Z
CE
1
1
goes low, CE2 going high and WE going low. A write end at
CE
going high, CE2 going low and WE going high. tWP is
1
going low or CE2 going high to the end of write.
t
C W
P. 8
t
CE , a high CE2 and a low WE . A write begins at
t
t
C W
A W
W H Z
t
W P
t
1
A W
t
t
W C
W C
t
W P
H i g h - Z
t
t
D W
D W
Publication Date: FEB. 2003
t
t
t
t
t
O W
W R
W R
D H
D H
T15N1024A
D O N ' T C A R E
D O N ' T C A R E
U N D E F I N E D
U N D E F I N E D
Revision:E