T15M256B TM tech, T15M256B Datasheet - Page 9

no-image

T15M256B

Manufacturer Part Number
T15M256B
Description
32K X 8 LOW POWER CMOS STATIC RAM
Manufacturer
TM tech
Datasheet
tm
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the
TM Technology Inc. reserves the right
to change products or specifications without notice.
2. The data output from
3.
4. Transition is measured
5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of
outputs should not be applied.
guaranteed but not 100% tested.
t WP or (t WHZ + t DW ) to allow the I/O drivers to turn off and data to be placed on the bus for the
required t DW .
not apply and the write pulse can be as short as the specified t WP .
D
CH
OUT
TE
provides the read data for the next address.
If OE is high during a WE controlled write cycle, this requirement does
D
OUT
500 mV from steady state with
are the same as the data written to
P. 9
C
L
= 5pF.
D
Publication Date: MAY. 2002
IN
This parameter is
during the write cycle.
T15M256B
Revision:A

Related parts for T15M256B