T1504 ACER, T1504 Datasheet - Page 16

• Manufacturer Part Number: T1504
• Description: COLOR TFT LCD MODULE
• Manufacturer: ACER

B
C
D
A
DESIG.
Table 10-3. Timing Characteristics
*1) DCLK signal input must be valid while power supply is applied.
*3) If a period of ENAB “High” is less than 512 DCLK or less than 768 lines, the rest of the screen
*4) The display position does not fit to the screen if the ENAB period and the effective data period
*2) Display position is specified by the ENAB signal.
DCLK signal
(Clock)
DCLK-Data
Timing
10-3. Input Signal Timing
do not synchronize with each other.
Horizontal
Vertical
Data-ENAB timing
displays black.
∙ Horizontal display position is specified by the rise of ENAB signal. The data of a horizontal
∙ Vertical display position is specified by the rise of ENAB after a “Low” level period equivalent
line, which is latched by the falling edge of 1st DCLK right after the rise of ENAB, is
displayed on the left edge of the screen.
to eight times of horizontal period. The 1st data corresponding to one horizontal line after
the rise of ENAB is displayed at the top line of screen.
Table 10-3 and Fig.10-3 shows the input signal timing.
1
1
Item
Period
Frequency
Duty
High time
Low time
Rise time
Fall time
Setup time
Hold time
Period
Frequency
Display period
Period
Frequency
Display period
CHECK
Symbol
Tch/Tc
TclkH
TclkL
Thold
Tclkr
Tclkf
2
Tset
Thd
Tvd
Th
Tv
Tc
—
fh
fv
fc
25.000
25.000
Min.
38.6
565
772
5.0
5.0
4.5
6.5
45
50
—
—
—
—
—
APPR.
30.764
32.505
Typ.
672
512
806
768
48
60
50
—
—
—
—
—
—
0
40.000
40.000
Max.
1566
868
5.0
5.0
60
55
75
—
—
—
—
—
—
—
Tech Bes LCD-00033
3
FLC38XGC6V-06
(T=0~50º
DCLK fh=1/Th
DCLK *2,3
DCLK *4
MHz
Unit
kHz
【FLC38XGC6V-06】
Th
Hz
Th
ns
％
ns
ns
ns
ns
ns
ns
C
fc=1/Tc
*1
40MHz
40MHz
16.67ms
*2,3
, Vcc=5±0.25V)
Remark
15
4
A
B
C
D
E
F