PIC18LF8720 Microchip Technology, PIC18LF8720 Datasheet - Page 65

no-image

PIC18LF8720

Manufacturer Part Number
PIC18LF8720
Description
(PIC18LF6620/6520/8520/6620/8620/6720/8720) 64/80-Pin High-Performance / 64-Kbyte Enhanced Flash Microcontrollers
Manufacturer
Microchip Technology
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF8720-I/PT
Manufacturer:
Vishay
Quantity:
9 195
Part Number:
PIC18LF8720-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18LF8720-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC18LF8720-I/PTC01
Manufacturer:
MICROCH
Quantity:
20 000
Part Number:
PIC18LF8720T-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
PIC18LF8720T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
REGISTER 5-1:
 2004 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIC18F6520/8520/6620/8620/6720/8720
EECON1 REGISTER (ADDRESS FA6h)
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access configuration registers
0 = Access Flash program or data EEPROM memory
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
0 = Perform write only
WRERR: Flash Program/Data EEPROM Error Flag bit
1 = A write operation is prematurely terminated
0 = The write operation completed
WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write
0 = Write cycle to the EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit
- n = Value at POR
EEPGD
R/W-x
Note:
(cleared by completion of erase operation)
(any Reset during self-timed programming in normal operation)
cycle. (The operation is self-timed and the bit is cleared by hardware once write is
complete. The WR bit can only be set (not cleared) in software.)
can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows
tracing of the error condition.
R/W-x
CFGS
U-0
W = Writable bit
‘1’ = Bit is set
R/W-0
FREE
WRERR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-x
WREN
R/W-0
x = Bit is unknown
R/S-0
WR
DS39609B-page 63
R/S-0
RD
bit 0

Related parts for PIC18LF8720